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CY62147EV30LL-45B2XI PDF预览

CY62147EV30LL-45B2XI

更新时间： 2024-11-19 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 382K
描述
4-Mbit (256K x 16) Static RAM

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CY62147EV30LL-45B2XI 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：VFBGA, BGA48,6X8,30
针数：48Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：1.98
Samacsys Description：Cypress Semiconductor, CY62147EV30LL-45B2XI SRAM Memory, 4Mbit, 45ns, 2.2 → 3.6 V 48-Pin FBGA最长访问时间：45 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B48
JESD-609代码：e1长度：8 mm
内存密度：4194304 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：48
字数：262144 words字数代码：256000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA48,6X8,30
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3 V认证状态：Not Qualified
座面最大高度：1 mm最大待机电流：0.00002 A
最小待机电流：1.5 V子类别：SRAMs
最大压摆率：0.02 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.2 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：6 mm

CY62147EV30LL-45B2XI 数据手册

 浏览型号CY62147EV30LL-45B2XI的Datasheet PDF文件第2页浏览型号CY62147EV30LL-45B2XI的Datasheet PDF文件第3页浏览型号CY62147EV30LL-45B2XI的Datasheet PDF文件第4页浏览型号CY62147EV30LL-45B2XI的Datasheet PDF文件第5页浏览型号CY62147EV30LL-45B2XI的Datasheet PDF文件第6页浏览型号CY62147EV30LL-45B2XI的Datasheet PDF文件第7页 
CY62147EV30 MoBL®  
4-Mbit (256K x 16) Static RAM  
ideal for providing More Battery Life™ (MoBL®) in portable appli-  
cations such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Placing the  
device into standby mode reduces power consumption by more  
than 99% when deselected (CE HIGH or both BLE and BHE are  
HIGH). The input and output pins (IO0 through IO15) are placed  
in a high impedance state when:  
Features  
■
Very high speed: 45 ns  
■
Temperature ranges  
❐
❐
❐
Industrial: –40°C to +85°C  
Automotive-A: –40°C to +85°C  
Automotive-E: –40°C to +125°C  
■
■
■
Wide voltage range: 2.20V to 3.60V  
Pin compatible with CY62147DV30  
Ultra low standby power  
■
■
■
Deselected (CE HIGH)  
Outputs are disabled (OE HIGH)  
Both Byte High Enable and Byte Low Enable are disabled  
(BHE, BLE HIGH)  
❐
Typical standby current: 1 μA  
❐
Maximum standby current: 7 μA (Industrial)  
■
Write operation is active (CE LOW and WE LOW)  
■
Ultra low active power  
Typical active current: 2 mA at f = 1 MHz  
Easy memory expansion with CE [1] and OE features  
Automatic power down when deselected  
CMOS for optimum speed and power  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from IO pins (IO0 through IO7) is written into the location  
specified on the address pins (A0 through A17). If Byte High  
❐
■
■
■
■
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15  
)
is written into the location specified on the address pins (A0  
through A17).  
AvailableinPb-free48-ballVFBGA(single/dualCEoption)and  
44-pin TSOPII packages  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appear on IO0 to IO7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on IO8 to IO15. See the Truth Table on page 9 for a  
complete description of read and write modes.  
■
Byte power down feature  
Functional Description  
The CY62147EV30 is a high performance CMOS static RAM  
organized as 256K words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. It is  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
9
A
A
8
A
7
6
5
4
3
A
A
A
256K x 16  
IO –IO  
0
7
RAM Array  
A
IO –IO  
8
15  
A
2
1
0
A
A
COLUMN DECODER  
BHE  
WE  
CE  
POWER DOWN  
CIRCUIT  
BHE  
BLE  
[1]  
CE  
OE  
BLE  
Note  
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE and  
1
CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH.  
2
1
2
Cypress Semiconductor Corporation  
Document #: 38-05440 Rev. *G  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Revised March 31, 2009  
[+] Feedback  
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CY62147EV30LL-45B2XI 替代型号

型号 品牌 替代类型 描述 数据表
CY62147EV30LL-45B2XIT CYPRESS

完全替代

 Standard SRAM, 256KX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62147EV30LL-45B2XA CYPRESS

完全替代

 Automotive 4-Mbit (256K x 16) Static RAM Wide voltage range: 2.20 V to 3.60 V

与CY62147EV30LL-45B2XI相关器件

型号 品牌 获取价格 描述 数据表
CY62147EV30LL-45B2XIT CYPRESS

获取价格

 		Standard SRAM, 256KX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62147EV30LL-45B2XIT INFINEON

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 		Asynchronous SRAM
CY62147EV30LL-45BVI CYPRESS

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 		4-Mbit (256K x 16) Static RAM
CY62147EV30LL-45BVIT CYPRESS

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 		Standard SRAM, 256KX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62147EV30LL-45BVXA CYPRESS

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 		4-Mbit (256K x 16) Static RAM
CY62147EV30LL-45BVXI CYPRESS

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 		4-Mbit (256K x 16) Static RAM
CY62147EV30LL-45BVXI INFINEON

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 		Asynchronous SRAM
CY62147EV30LL-45BVXIT CYPRESS

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 		Standard SRAM, 256KX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM PITCH, ROHS COMPLIANT, VFBGA-48
CY62147EV30LL-45BVXIT INFINEON

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 		Asynchronous SRAM
CY62147EV30LL-45ZSXA CYPRESS

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 		4-Mbit (256K x 16) Static RAM

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