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CY62147EV30AUTO PDF预览

CY62147EV30AUTO

更新时间: 2024-11-19 09:42:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
15页 507K
描述
Automotive 4-Mbit (256K x 16) Static RAM Wide voltage range: 2.20 V to 3.60 V

CY62147EV30AUTO 数据手册

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CY62147EV30 MoBL®  
Automotive 4-Mbit (256K x 16) Static RAM  
also has an automatic power down feature that significantly  
reduces power consumption when addresses are not toggling.  
Placing the device into standby mode reduces power  
consumption by more than 99 percent when deselected (CE  
HIGH or both BLE and BHE are HIGH). The input and output pins  
(I/O0 through I/O15) are placed in a high impedance state when:  
Features  
Very high speed: 45 ns  
Temperature ranges  
Automotive-A: –40 °C to +85 °C  
Automotive-E: –40 °C to +125 °C  
Deselected (CE HIGH)  
Wide voltage range: 2.20 V to 3.60 V  
Pin compatible with CY62147DV30  
Ultra low standby power  
Outputs are disabled (OE HIGH)  
Both Byte High Enable and Byte Low Enable are disabled  
(BHE, BLE HIGH)  
Typical standby current: 1 A  
Maximum standby current: 7 A (Automotive-A)  
Ultra low active power  
Write operation is active (CE LOW and WE LOW)  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7) is written into the location  
specified on the address pins (A0 through A17). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A17).  
Typical active current: 2 mA (Automotive-A) at f = 1 MHz  
Easy memory expansion with CE [1] and OE features  
Automatic power down when deselected  
Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appear on I/O0 to I/O7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on I/O8 to I/O15. See the Truth Table on page 10 for a  
complete description of read and write modes.  
Available in Pb-free 48-ball very fine ball grid array (VFBGA)  
(single/dual CE option) and 44-pin thin small outline package  
(TSOP) II packages  
Byte power-down feature  
Functional Description  
The CY62147EV30 is a high performance CMOS static RAM  
(SRAM) organized as 256K words by 16 bits. This device  
features advanced circuit design to provide ultra low active  
current. It is ideal for providing More Battery Life™ (MoBL) in  
portable applications such as cellular telephones. The device  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
256K x 16  
I/O0–I/O7  
RAM Array  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE  
POWER DOWN  
CIRCUIT  
BHE  
BLE  
[1]  
CE  
OE  
BLE  
Note  
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE and  
1
CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH.  
2
1
2
Cypress Semiconductor Corporation  
Document Number: 001-66256 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 31, 2011  
[+] Feedback  

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