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CY62146V18LL-70BAI

更新时间： 2024-11-18 23:45:07
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器
页数 文件大小 规格书
11页 239K
描述
x16 SRAM

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中文翻译

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CY62146V18LL-70BAI 数据手册

 浏览型号CY62146V18LL-70BAI的Datasheet PDF文件第2页浏览型号CY62146V18LL-70BAI的Datasheet PDF文件第3页浏览型号CY62146V18LL-70BAI的Datasheet PDF文件第4页浏览型号CY62146V18LL-70BAI的Datasheet PDF文件第5页浏览型号CY62146V18LL-70BAI的Datasheet PDF文件第6页浏览型号CY62146V18LL-70BAI的Datasheet PDF文件第7页 
CY62146V MoBL™  
CY62146V18 MoBL2™  
256K x 16 Static RAM  
put/output pins (I/O through I/O ) are placed in a high-im-  
Features  
0
15  
pedance state when: deselected (CE HIGH), outputs are dis-  
abled (OE HIGH), BHE and BLE are disabled (BHE, BLE  
HIGH), or during a write operation (CE LOW, and WE LOW).  
• Low voltage range:  
— CY62146V18: 1.65V–1.95V  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
— CY62146V: 2.7V–3.6V  
• Ultra-low active, standby power  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
0
7
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
written into the location specified on the address pins (A  
0
through A ). If Byte High Enable (BHE) is LOW, then data  
16  
from I/O pins (I/O through I/O ) is written into the location  
8
15  
specified on the address pins (A through A ).  
0
17  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
Functional Description  
The CY62146V and CY62146V18 are high-performance  
CMOS static RAMs organized as 262,144 words by 16 bits.  
These devices feature advanced circuit design to provide ul-  
tra-low active current. This is ideal for providing More Battery  
Life™ (MoBL™) in portable applications such as cellular tele-  
phones. The device also has an automatic power-down fea-  
ture that significantly reduces power consumption by 99%  
when addresses are not toggling. The device can also be put  
into standby mode when deselected (CE HIGH). The in-  
will appear on I/O to I/O . If Byte High Enable (BHE) is LOW,  
0
7
then data from memory will appear on I/O to I/O . See the  
8
15  
truth table at the back of this data sheet for a complete descrip-  
tion of read and write modes.  
The CY62146V and CY62146V18 are available in 48-Ball  
FBGA and standard 44-Pin TSOP Type II (forward pinout)  
packaging.  
Logic Block Diagram  
Pin  
Configurations  
TSOP II (Forward)  
Top View  
44  
1
A
4
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
DATA IN DRIVERS  
A
A
2
7
OE  
A
1
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
BHE  
BLE  
I/O  
I/O  
I/O  
A
0
CE  
I/O  
7
0
15  
37  
36  
35  
34  
33  
I/O  
I/O  
8
1
2
14  
13  
12  
256K x 16  
9
10  
11  
12  
13  
I/O  
V
SS  
RAM Array  
2048 x 2048  
I/O  
I/O0–I/O7  
3
CC  
V
SS  
V
V
I/O8–I/O15  
CC  
I/O  
32  
I/O  
I/O  
4
5
6
7
11  
10  
A1  
A0  
I/O  
I/O  
I/O  
31  
30  
29  
28  
14  
15  
16  
I/O  
I/O  
9
8
WE 17  
NC  
18  
27  
26  
25  
A
A
8
16  
19  
A
A
9
COLUMN DECODER  
15  
A
A
A
20  
21  
22  
A
14  
10  
A
24  
23  
11  
13  
A
12  
17  
BHE  
WE  
CE  
OE  
62146V–2  
BLE  
62146V–1  
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
March 23, 2000  
1234567...11

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