Datasheet > CY62146V18-85BAI

CY62146V18-85BAI

更新时间： 2024-11-18 23:45:07

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
10页	154K
描述
x16 SRAM

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CY62146V18-85BAI 数据手册

CY62146V18 MoBL2™

256K x 16 Static RAM

I/O ) are placed in a high-impedance state when deselected

Features

(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW, and WE LOW).

• Low voltage range:

— CY62146V18: 1.75V–1.95V

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

• Ultra-low active, standby power

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

(BLE) is LOW, then data from I/O pins (I/O through I/O ), is

written into the location specified on the address pins (A

through A ). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O through I/O ) is written into the location

specified on the address pins (A through A ).

Functional Description

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then

data from the memory location specified by the address pins

The CY62146V18 is a high-performance CMOS static RAM

organized as 262,144 words by 16 bits. These devices feature

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL™) in por-

table applications such as cellular telephones. The device also

has an automatic power-down feature that significantly reduc-

es power consumption by 99% when addresses are not tog-

gling. The device can also be put into standby mode when

will appear on I/O to I/O . If Byte High Enable (BHE) is LOW,

then data from memory will appear on I/O to I/O . See the

truth table at the back of this data sheet for a complete descrip-

tion of read and write modes.

The CY62146V18 is available in 48-Ball FBGA packaging.

deselected (CE HIGH). The input/output pins (I/O through

Logic Block Diagram

DATA IN DRIVERS

A₉

A₈

A₇

A₆

A₅

A₄

A₃

256K x 16

RAM Array

2048 x 2048

I/O₀–I/O₇

I/O₈–I/O₁₅

A₂

A₁

A₀

COLUMN DECODER

BHE

BLE

MoBL2 and More Battery Life are trademarks of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

September 6, 2000

12 3 4 5 6 7...10

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与CY62146V18-85BAI相关器件

型号	品牌	获取价格	描述	数据表
CY62146V18LL-70BAI	ETC	获取价格	x16 SRAM
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CY62146VLL-70ZI	CYPRESS	获取价格	4M (256K x 16) Static RAM
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CY621472E30LL-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY621472E30LL-45ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY621472G30-45ZSXA	INFINEON	获取价格	Asynchronous SRAM
CY621472G30-45ZSXAT	INFINEON	获取价格	Asynchronous SRAM
CY621472G30-45ZSXI	CYPRESS	获取价格	Standard SRAM, 256KX16, 45ns, CMOS, PDSO44, TSOP2-44
CY621472G30-45ZSXI	INFINEON	获取价格	Asynchronous SRAM

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