Datasheet > CY62146GN30-45ZSXI

CY62146GN30-45ZSXI

更新时间： 2024-11-06 14:56:35

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
16页	478K
描述
Asynchronous SRAM

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CY62146GN MoBL^®

4-Mbit (256K × 16) Static RAM

4-Mbit (256K

× 16) Static RAM

Features

Functional Description

■ Very high speed: 45 ns

■ Temperature ranges

The CY62146GN is a high performance CMOS static RAM

organized as 256K words by 16 bits. This device features an

advanced circuit design designed to provide an ultra low active

current. Ultra low active current is ideal for providing More

Battery Life (MoBL^®) in portable applications such as cellular

telephones. The device also has an automatic power down

feature that significantly reduces power consumption by 80

percent when addresses are not toggling.The device can also be

put into standby mode reducing power consumption by more

than 99 percent when deselected (CE HIGH). The input and

output pins (I/O₀through I/O₁₅) are placed in a high impedance

state when the device is deselected (CE HIGH), outputs are

disabled (OE HIGH), both Byte High Enable and Byte Low

Enable are disabled (BHE, BLE HIGH), or a write operation is in

progress (CE LOW and WE LOW).

❐ Industrial: –40 °C to +85 °C

■ Wide voltage range: 2.20 V to 3.60 V and 4.5 V to 5.5 V

■ Ultra low standby power

❐ Typical standby current: 3.5 A

❐ Maximum standby current: 8.7 A

■ Ultra low active power

❐ Typical active current: 3.5 mA at f = 1 MHz

■ Automatic power down when deselected

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

To write to the device, take Chip Enable (CE) and Write Enable

(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (I/O₀through I/O₇) is written into the location

specified on the address pins (A₀through A₁₇). If Byte High

Enable (BHE) is LOW, then data from the I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₇).

■ Available in a 44-pin TSOP II and 48-ball VFBGA Packages

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appears on I/O₀to I/O₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on I/O₈to I/O₁₅. See the Truth Table on page 11 for a

complete description of read and write modes.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

256K x 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 001-95417 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 15, 2017

12 3 4 5 6 7...16

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与CY62146GN30-45ZSXI相关器件

型号	品牌	获取价格	描述	数据表
CY62146V	ETC	获取价格	Memory
CY62146V18-85BAI	ETC	获取价格	x16 SRAM
CY62146V18LL-70BAI	ETC	获取价格	x16 SRAM
CY62146VLL-70BAI	ETC	获取价格	x16 SRAM
CY62146VLL-70ZI	CYPRESS	获取价格	4M (256K x 16) Static RAM
CY621472E30LL-45ZSXI	CYPRESS	获取价格	Standard SRAM, 256KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY621472E30LL-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY621472E30LL-45ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY621472G30-45ZSXA	INFINEON	获取价格	Asynchronous SRAM
CY621472G30-45ZSXAT	INFINEON	获取价格	Asynchronous SRAM

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