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CY62137FV18LL-55BVXI PDF预览

CY62137FV18LL-55BVXI

更新时间: 2024-11-06 14:56:19
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
16页 409K
描述
Asynchronous SRAM

CY62137FV18LL-55BVXI 数据手册

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CY62137FV18 MoBL®  
2-Mbit (128 K × 16) Static RAM  
2-Mbit (128  
K × 16) Static RAM  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Placing the  
device into standby mode reduces power consumption by more  
than 99% when deselected (CE HIGH or both BLE and BHE are  
HIGH). The input and output pins (I/O0 through I/O15) are placed  
in a high impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), both the Byte High  
Enable and the Byte Low Enable are disabled (BHE, BLE HIGH),  
or during an active write operation (CE LOW and WE LOW).  
Features  
Very high speed: 55 ns  
Wide voltage range: 1.65 V to 2.25 V  
Pin compatible with CY62137CV18  
Ultra low standby power  
Typical standby current: 1 A  
Maximum standby current: 5 A  
Ultra low active power  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7) is written into the location  
specified on the address pins (A0 through A16). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A16).  
Typical active current: 1.6 mA @ f = 1 MHz  
Easy memory expansion with CE and OE features  
Automatic power down when deselected  
Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
Byte power-down feature  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appear on I/O0 to I/O7. If  
Byte High Enable (BHE) is LOW, then data from the memory  
appears on I/O8 to I/O15. See the Truth Table on page 11 for a  
complete description of read and write modes.  
Available in a Pb-free 48-ball Very fine-pitch ball grid package  
(VFBGA) package  
Functional Description  
The CY62137FV18 is a high performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL) in portable  
For a complete list of related documentation, click here.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
128K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
POWER DOWN  
CIRCUIT  
BHE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 001-08030 Rev. *M  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 29, 2017  

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