Datasheet > CY62137FV18LL-55BVXI

CY62137FV18LL-55BVXI

更新时间： 2024-11-21 14:56:19

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
16页	409K
描述
Asynchronous SRAM

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中文翻译

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数据手册

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CY62137FV18LL-55BVXI 数据手册

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CY62137FV18 MoBL^®

2-Mbit (128 K × 16) Static RAM

2-Mbit (128

K × 16) Static RAM

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption when addresses are not toggling. Placing the

device into standby mode reduces power consumption by more

than 99% when deselected (CE HIGH or both BLE and BHE are

HIGH). The input and output pins (I/O₀through I/O₁₅) are placed

in a high impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), both the Byte High

Enable and the Byte Low Enable are disabled (BHE, BLE HIGH),

or during an active write operation (CE LOW and WE LOW).

Features

■ Very high speed: 55 ns

■ Wide voltage range: 1.65 V to 2.25 V

■ Pin compatible with CY62137CV18

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 5 A

■ Ultra low active power

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (I/O₀through I/O₇) is written into the location

specified on the address pins (A₀through A₁₆). If Byte High

Enable (BHE) is LOW, then data from I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₆).

❐ Typical active current: 1.6 mA @ f = 1 MHz

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■ Byte power-down feature

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appear on I/O₀to I/O₇. If

Byte High Enable (BHE) is LOW, then data from the memory

appears on I/O₈to I/O₁₅. See the Truth Table on page 11 for a

complete description of read and write modes.

■ Available in a Pb-free 48-ball Very fine-pitch ball grid package

(VFBGA) package

Functional Description

The CY62137FV18 is a high performance CMOS static RAM

organized as 128K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

For a complete list of related documentation, click here.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

128K x 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

COLUMN DECODER

BHE

BLE

POWER DOWN

CIRCUIT

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 001-08030 Rev. *M

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 29, 2017

12 3 4 5 6 7...16

中文翻译

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与CY62137FV18LL-55BVXI相关器件

型号	品牌	获取价格	描述	数据表
CY62137FV18LL-55BVXIT	CYPRESS	获取价格	Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62137FV18LL-55BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62137FV30	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137FV30_08	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137FV30_09	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137FV30_11	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137FV30_1106	CYPRESS	获取价格	2-Mbit (128 K x 16) Static RAM Automatic power down when deselected
CY62137FV30LL	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137FV30LL-45BVI	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62137FV30LL-45BVIT	CYPRESS	获取价格	Standard SRAM, 128KX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48

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