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CY54FCT543TLMB PDF预览

CY54FCT543TLMB

更新时间： 2024-01-07 15:03:51
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
12页 316K
描述
8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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中文翻译

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CY54FCT543TLMB 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QLCC
包装说明：CERAMIC, LCC-28针数：28
Reach Compliance Code：not_compliant风险等级：5.36
Is Samacsys：N其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：FCTJESD-30 代码：S-CQCC-N28
JESD-609代码：e0长度：11.43 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.048 A位数：8
功能数量：1端口数量：2
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装等效代码：LCC28,.45SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
Prop。Delay @ Nom-Sup：10 ns传播延迟（tpd）：14 ns
认证状态：Not Qualified筛选级别：38535Q/M;38534H;883B
座面最大高度：1.9812 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：11.43 mmBase Number Matches：1

CY54FCT543TLMB 数据手册

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CY54FCT543T, CY74FCT543T  
8-BIT LATCHED REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCCS030A – MAY 1994 – REVISED OCTOBER 2001  
CY54FCT543T . . . D PACKAGE  
CY74FCT543T . . . Q OR SO PACKAGE  
(TOP VIEW)  
Function, Pinout, and Drive Compatible  
With FCT and F Logic  
Reduced V  
of Equivalent FCT Functions  
(Typically = 3.3 V) Versions  
OH  
LEBA  
OEBA  
1
24  
V
CC  
2
23 CEBA  
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
A
A
A
A
A
A
A
A
3
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
B
B
B
B
B
B
B
B
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4
5
I
Supports Partial-Power-Down Mode  
off  
6
Operation  
7
Matched Rise and Fall Times  
8
Fully Compatible With TTL Input and  
Output Logic Levels  
9
10  
11  
12  
3-State Outputs  
CEAB  
GND  
LEAB  
OEAB  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
Separation Controls for Data Flow in Each  
Direction  
Back-to-Back Latches for Storage  
CY54FCT543T  
– 48-mA Output Sink Current  
– 12-mA Output Source Current  
CY74FCT543T  
– 64-mA Output Sink Current  
– 32-mA Output Source Current  
description  
The ’FCT543T octal latched transceivers contain two sets of eight D-type latches with separate latch-enable  
(LEAB, LEBA) and output-enable (OEAB, OEBA) inputs for each set to permit independent control of input and  
output in either direction of data flow. For data flow from A to B, for example, the A-to-B enable (CEAB) input  
must be low in order to enter data from A or to take data from B, as indicated in the function table. With CEAB  
low, a low signal on the A-to-B latch-enable (LEAB) input makes the A-to-B latches transparent; a subsequent  
low-to-high transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer  
change with the A inputs. With CEAB and OEAB low, the 3-state B-output buffers are active and reflect the data  
present at the output of the A latches. Control of data from B to A is similar, but uses CEBA, LEBA, and OEBA  
inputs.  
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the  
off  
off  
outputs, preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
unless otherwise noted. On all other products, production  
testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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