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CY54FCT543ATDMB PDF预览

CY54FCT543ATDMB

更新时间： 2024-01-22 09:10:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
8页 144K
描述
Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, CDIP24, 0.300 INCH, CERDIP-24

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CY54FCT543ATDMB 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QLCC
包装说明：CERAMIC, LCC-28针数：28
Reach Compliance Code：not_compliant风险等级：5.36
Is Samacsys：N其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：FCTJESD-30 代码：S-CQCC-N28
JESD-609代码：e0长度：11.43 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.048 A位数：8
功能数量：1端口数量：2
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装等效代码：LCC28,.45SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
Prop。Delay @ Nom-Sup：10 ns传播延迟（tpd）：14 ns
认证状态：Not Qualified筛选级别：38535Q/M;38534H;883B
座面最大高度：1.9812 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：11.43 mmBase Number Matches：1

CY54FCT543ATDMB 数据手册

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1CY54/74FCT543T  
fax id: 7040  
CY54/74FCT543T  
8-Bit Latched Registered Transceiver  
Features  
Functional Description  
• Function, pinout, and drive compatible with FCT and  
The FCT543T octal latched transceiver contains two sets of  
eight D-type latches with separate latch enable (LEAB, LEBA)  
and output enable (OEAB, OEBA) controls for each set to  
permit independent control of inputting and outputting in either  
direction of data flow. For data flow from A to B, for example,  
the A-to-B enable (CEAB) input must be LOW in order to enter  
data from A or to take data from B, as indicated in the truth  
table. With CEAB LOW, a LOW signal on the A-to-B latch  
enable (LEAB) input makes the A-to-B latches transparent; a  
subsequent LOW-to-HIGH transition of the LEAB signal puts  
the A latches in the storage mode and their output no longer  
change with the A inputs. With CEAB and OEAB both LOW,  
the three-stage B output buffers are active and reflect the data  
present at the output of the A latches. Control of data from B  
to A is similar, but uses CEAB, LEAB, and OEAB inputs.  
F logic  
• FCT-C speed at 5.3 ns max. (Com’l)  
FCT-A speed at 6.5 ns max. (Com’l)  
• Reduced V  
(typically = 3.3V) versions of equivalent  
OH  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Power-off disable feature  
• Matched rise and fall times  
• Fully compatible with TTL input and output logic levels  
• ESD > 2000V  
• Sink current  
Source current  
64 mA (Com’l), 48 mA (Mil)  
32 mA (Com’l), 12 mA (Mil)  
• Separation controls for data flow in each direction  
• Back to back latches for storage  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
• Extended commercial range of −40°C to +85°C  
Functional Block Diagram  
Logic Block Diagram  
Detail A  
B
D Q  
LE  
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CEAB  
OEAB  
A
0
Q D  
LE  
CEBA  
LEAB  
LEBA  
OEBA  
A
B
B
B
B
B
B
B
1
1
2
3
4
5
6
7
B
B
B
B
B
B
B
B
7
0
1
2
3
4
5
6
A
2
A
3
A
4
DetailA x 7  
A
5
A
6
Pin Configurations  
A
7
SOIC/QSOP  
Top View  
OEBA  
OEAB  
1
LEBA  
OEBA  
24  
23  
22  
21  
CEBA  
LEBA  
V
CC  
2
CEBA  
CEAB  
LEAB  
3
A
0
B
0
4
A
1
B
1
A
2
5
B
2
20  
19  
A
3
6
B
3
A
4
B
4
7
18  
17  
16  
A
5
B
5
8
A
6
B
6
9
A
7
B
7
10  
11  
12  
15  
14  
CEAB  
GND  
LEAB  
OEAB  
13  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
May 1994 – Revised March 17, 1997  
12345678

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