Datasheet > CY39200V676-167MBC

CY39200V676-167MBC

更新时间： 2024-11-26 10:50:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
57页	1166K
描述
Loadable PLD, 8.5ns, CMOS, PBGA676, 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676

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Delta39K™ ISR™

CPLD Family

PRELIMINARY

CPLDs at FPGA Densities™

•Multiple I/O standards supported

Features

—LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2

•High density

(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

— 15K to 350K usable gates

— 256 to 5376 macrocells

— 92 to 520 maximum I/O pins

•Compatible with NOBL™, ZBT™, and QDR™ SRAMs

•Programmable slew rate control on each I/O pin

•User-Programmable Bus Hold capability on each I/O pin

•Fully PCI compliant (to 66 MHz 64-bit PCI spec rev2.2)

•Compact PCI hot swap compatible

•Multiple package/pinout offering across all densities

—144 to 676 pins in PQFP, BGA and FBGA packages

—Same pinout for 3.3V/2.5V and 1.8V devices

—Simplifies design migration across density

—Self-Boot™ solution in BGA and FBGA packages

•In-System Reprogrammable™ (ISR™)

— 12 Dedicated Inputs including 4 clock pins, 4 global

control signal pins and 4 JTAG interface pins for

reconfigurability

•Embedded Memory

— 40K to 840K bits embedded SRAM

• 32K to 672K bits of (single port) Cluster memory

• 8K to 168K bits of (dual port) Channel memory

•High speed - 250-MHz in-system operation

•AnyVolt™ interface

—JTAG-compliant on-board programming

— 3.3V, 2.5V and 1.8V V_CCversions available

—Design changes don’t cause pinout changes

•IEEE1149.1 JTAG boundary scan

— 3.3V, 2.5V and 1.8V I/O capability on all versions

• Low Power Operation

— 0.18-µm 6-layer metal SRAM-based logic process

— Full-CMOS implementation of product term array

Development Software

— Standby current as low as 100 µA at 1.8V V_CC

•Simple timing model

•Warp™

—IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

sensitive editing.

— Nopenaltyfor usingfull16product terms /macrocell

— No delay for single product term steering or sharing

•Flexible clocking

—Active-HDL FSM graphical finite state machine editor

—Active-HDL SIM post-synthesis timing simulator

—Architecture Explorer for detailed design analysis

—Static Timing Analyzer for critical path analysis

—Available on Windows 95, 98 & NT for $99

— 4 synchronous clocks per device

— 1 spread-aware PLL drives all 4 clock networks

— Locally generated Product Term clock

— Clock polarity control at each register

—Supports all Cypress Programmable Logic Products

•Carry-chain logic for fast and efficient arithmetic opera-

tions

Delta39K™ ISR CPLD Family Members

[2]

Standby I_CC

Cluster Channel

memory memory Maximum

f_MAX2Speed-t_PD

Pin-to-Pin

T_A=25°C

Typical

Gates^[1]

Device

39K15

Macrocells

256

(Kbits)

I/O Pins

(MHz)

256

238

222

181

167

154

(ns)

6.5

7.0

7.5

8.5

9.0

3.3/2.5V

1.8V

8K–24K

16K–48K

134

10 mA

100 µA

200 µA

300 µA

600 µA

1250 µA

1500 µA

2100 µA

39K30

512

176

39K50

23K–72K

768

218

39K100

39K165

39K200

39K250

39K350

46K–144K

77K–241K

92K–288K

115K–361K

161K–505K

1536

2560

3072

3840

5376

192

320

384

480

672

302

386

428

120

168

470

520

Note:

1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.

2. Standby I_CCvalues are with PLL not utilized, no output load and stable inputs

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-03039 Rev. **

Revised April 4, 2001

12 3 4 5 6 7...57

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与CY39200V676-167MBC相关器件

型号	品牌	获取价格	描述	数据表
CY39200V676-181MBXC	CYPRESS	获取价格	Loadable PLD, 8.5ns, CMOS, PBGA676, 27 X 27 MM, 1.6 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA
CY39200Z208-125BBC	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125BBI	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125BGC	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125BGI	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125MBC	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125MBI	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125MGC	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125MGI	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125NC	CYPRESS	获取价格	CPLDs at FPGA Densities

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