Datasheet > CY39200V676-125MBXC

CY39200V676-125MBXC

更新时间： 2024-11-26 05:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
86页	2652K
描述
Loadable PLD, 10ns, CMOS, PBGA676, 27 X 27 MM, 1.6 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-676

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Delta39K™ ISR™

CPLD Family

CPLDs at FPGA Densities™

• Multiple I/O standards supported

Features

—LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2

(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

• High density

— 30K to 200K usable gates

— 512 to 3072 macrocells

— 136 to 428 maximum I/O pins

• Compatible with NOBL™, ZBT™, and QDR™ SRAMs

• Programmable slew rate control on each I/O pin

• User-programmable Bus Hold capability oneach I/O pin

— Twelve dedicated inputs including four clock pins,

four global I/O control signal pins and four JTAG

interface pins for boundary scan and reconfig-

urability

• Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,

rev. 2.2)

• CompactPCI hot swap ready

• Multiple package/pinout offering across all densities

— 208 to 676 pins in PQFP, BGA, and FBGA packages

—Simplifies design migration across density

— Self-Boot™ solution in BGA and FBGA packages

— Lead (Pb)-free packages available.

• Embedded memory

— 80K to 480K bits embedded SRAM

• 16K to 96K bits of (dual-port) channel memory

• High speed – 233-MHz in-system operation

• AnyVolt™ interface

• In-System Reprogrammable™ (ISR™)

— 3.3V, 2.5V,1.8V, and 1.5V I/O capability

• Low-power operation

— JTAG-compliant on-board programming

— Design changes do not cause pinout changes

• IEEE1149.1 JTAG boundary scan

— 0.18-mm six-layer metal SRAM-based logic process

— Full-CMOS implementation of product term array

— Standby current as low as 5mA

Development Software

• Simple timing model

• Warp^®

— No penalty for using full 16 product terms/macrocell

— No delay for single product term steering or sharing

• Flexible clocking

— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

sensitive editing

— Spread Aware™ PLL drives all four clock networks

• Allows 0.6% spread spectrum input clocks

• Several multiply, divide and phase shift options

— Four synchronous clock networks per device

—Locally generated product term clock

— Clock polarity control at each register

— Active-HDL FSM graphical finite state machine editor

— Active-HDL SIM post-synthesis timing simulator

— Architecture Explorer for detailed design analysis

— Static Timing Analyzer for critical path analysis

— Available on Windows^®95/98/2000/XP™ and

Windows NT™ for $99

— Supports all Cypress programmable logic products

• Carry-chain logic for fast and efficient arithmetic opera-

tions

Delta39K™ ISR CPLD Family Members

[2]

Standby I_CC

Cluster Channel

Speed-t_PD

T_A= 25°C

3.3/2.5V

5 mA

Typical

Gates^[1]

memory memory Maximum f_MAX2Pin-to-Pin

Device

39K30

Macrocells

512

(Kbits)

I/O Pins

174

(MHz)

233

(ns)

7.2

7.5

8.5

16K – 48K

23K – 72K

46K – 144K

92K – 288K

39K50

768

218

233

5 mA

39K100

39K200

1536

192

384

302

222

10 mA

20 mA

3072

428

181

Notes:

1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.

2. Standby I values are with PLL not utilized, no output load and stable inputs.

Cypress Semiconductor Corporation

Document #: 38-03039 Rev. *I

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised March 11, 2005

12 3 4 5 6 7...86

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与CY39200V676-125MBXC相关器件

型号	品牌	获取价格	描述	数据表
CY39200V676-167MBC	CYPRESS	获取价格	Loadable PLD, 8.5ns, CMOS, PBGA676, 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676
CY39200V676-181MBXC	CYPRESS	获取价格	Loadable PLD, 8.5ns, CMOS, PBGA676, 27 X 27 MM, 1.6 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA
CY39200Z208-125BBC	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125BBI	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125BGC	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125BGI	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125MBC	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125MBI	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125MGC	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39200Z208-125MGI	CYPRESS	获取价格	CPLDs at FPGA Densities

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