Datasheet > CY39030Z208-233NC

CY39030Z208-233NC

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
56页	1166K
描述
Loadable PLD, 7.2ns, 512-Cell, CMOS, PQFP208, PLASTIC, QFP-208

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Delta39K™ ISR™

CPLD Family

PRELIMINARY

CPLDs at FPGA Densities™

• Multiple I/O standards supported

Features

—LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2

• High density

(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

— 30K to 350K usable gates

— 512 to 5376 macrocells

— 136 to 520 maximum I/O pins

• Compatible with NOBL™, ZBT™, and QDR™ SRAMs

• Programmable slew rate control on each I/O pin

• User-Programmable Bus Hold capability on each I/O

• Fully PCI compliant (to 66 MHz 64-bit PCI spec rev2.2)

• CompactPCI hot swap ready

— 12 Dedicated Inputs including 4 clock pins, 4 global

I/O control signal pins and 4 JTAG interface pins for

boundary scan & reconfigurability

• Embedded Memory

• Multiple package/pinout offering across all densities

—208 to 676 pins in PQFP, BGA and FBGA packages

—Same pinout for 3.3V/2.5V and 1.8V devices

—Simplifies design migration across density

—Self-Boot™ solution in BGA and FBGA packages

• In-System Reprogrammable™ (ISR™)

— 80K to 840K bits embedded SRAM

• 64K to 672K bits of (single port) Cluster memory

• 16K to 168K bits of (dual port) Channel memory

• High speed – 233-MHz in-system operation

• AnyVolt™ interface

— 3.3V, 2.5V, and 1.8V V_CCversions available

—JTAG-compliant on-board programming

— 3.3V, 2.5V, and 1.8V I/O capability on all versions

• Low Power Operation

—Design changes don’t cause pinout changes

• IEEE1149.1 JTAG boundary scan

— 0.18-µm 6-layer metal SRAM-based logic process

— Full-CMOS implementation of product term array

Development Software

— Standby current as low as 200 µA at 1.8V V_CC

• Simple timing model

• Warp®

—IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

— Nopenaltyfor usingfull16product terms /macrocell

— No delay for single product term steering or sharing

• Flexible clocking

sensitive editing.

—Active-HDL FSM graphical finite state machine editor

—Active-HDL SIM post-synthesis timing simulator

—Architecture Explorer for detailed design analysis

—Static Timing Analyzer for critical path analysis

— 4 synchronous clocks per device

— 1 spread-aware PLL drives all 4 clock networks

— Locally generated Product Term clock

— Clock polarity control at each register

—Available on Windows 95™, Windows 98™ &

Windows NT™ for $99

• Carry-chain logic for fast and efficient arithmetic oper-

ations

—Supports all Cypress programmable logic products

Delta39K™ ISR CPLD Family Members

[2]

Standby I_CC

Cluster Channel

memory memory Maximum

f_MAX2Speed-t_PD

Pin-to-Pin

T_A=25°C

Typical

Gates^[1]

Device

39K30

Macrocells

512

(Kbits)

I/O Pins

(MHz)

233

222

181

167

154

(ns)

7.2

7.5

8.5

9.0

3.3/2.5V

1.8V

16K–48K

23K–72K

176

10 mA

200 µA

300 µA

600 µA

1250 µA

1500 µA

2100 µA

39K50

768

218

39K100

39K165

39K200

39K250

39K350

46K–144K

77K–241K

92K–288K

115K–361K

161K–505K

1536

192

320

384

480

672

302

2560

386

3072

428

3840

120

168

470

5376

520

Note:

1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.

2. Standby I_CCvalues are with PLL not utilized, no output load and stable inputs

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-03039 Rev. *A

Revised July 5, 2001

12 3 4 5 6 7...56

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与CY39030Z208-233NC相关器件

型号	品牌	获取价格	描述	数据表
CY39030Z256-125BBC	CYPRESS	获取价格	Loadable PLD, 10ns, 512-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256
CY39030Z256-125BBI	CYPRESS	获取价格	Loadable PLD, 10ns, 512-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256
CY39030Z256-125MBI	CYPRESS	获取价格	暂无描述
CY39030Z256-222MBC	CYPRESS	获取价格	Loadable PLD, 7ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-256
CY39030Z256-233BBC	CYPRESS	获取价格	Loadable PLD, 7.2ns, 512-Cell, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBG
CY39030Z256-233MBC	CYPRESS	获取价格	Loadable PLD, 7.2ns, 512-Cell, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBG
CY39030Z256-83BBI	CYPRESS	获取价格	Loadable PLD, 15ns, 512-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256
CY39030Z388-125BBC	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39030Z388-125BBI	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39030Z484-125BBC	CYPRESS	获取价格	CPLDs at FPGA Densities

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