Datasheet > CY38100V208B-125NI

CY38100V208B-125NI

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
32页	945K
描述
Loadable PLD, 10ns, CMOS, PQFP208, PLASTIC, QFP-208

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中文翻译

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数据手册

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Quantum38K™ ISR™

CPLD Family

PRELIMINARY

CPLDs at ASIC Prices™

• Multiple I/O standards supported:

Features

—LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI

• Compatible with NOBL™, ZBT™, and QDR™ SRAMs

• Programmable slew rate control on each I/O pin

• User-ProgrammableBusHoldcapabilityoneachI/Opin

• Fully PCI compliant (as per PCI spec rev. 2.2)

• Compact PCI hot swap ready

• Multiple package/pinout offering across all densities

—208 to 484 pins in PQFP and FBGA packages

—Simplifies design migration across density

• In-System Reprogrammable™ (ISR™)

• High density

— 30K to 100K usable gates

— 512 to 1536 macrocells

— 136 to 302 maximum I/O pins

— 8 Dedicated Inputs including 4 clock pins and 4

global I/O control signal pins; 4 JTAG interface pins

for reconfigurability/boundary scan

• Embedded Memory

— 16K to 48K bits embedded dual-port Channel mem-

ory

—JTAG-compliant on-board configuration

• 125 MHz in-system operation

• AnyVolt™ interface

—Design changes don’t cause pinout changes

• IEEE1149.1 JTAG boundary scan

— 3.3V and 2.5V V_CCoperation

• Pin-to-pin compatible with Cypress’s high-end

Delta39K CPLDs

— 3.3V, 2.5V and 1.8V I/O capability

• Low Power Operation

— 0.18-µm 6-layer metal SRAM-based logic process

Development Software

— Full-CMOS implementation of product term array

• Simple timing model

— Nopenaltyfor usingfull16product terms /macrocell

— No delay for single product term steering or sharing

• Flexible clocking

• Warp®

—IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

sensitive editing

—Active-HDL FSM graphical finite state machine editor

—Active-HDL SIM post-synthesis timing simulator

—Architecture Explorer for detailed design analysis

—Static Timing Analyzer for critical path analysis

— 4 synchronous clocks per device

— Locally generated Product Term clock

— Clock polarity control at each register

• Carry-chain logic for fast and efficient arithmetic oper-

ations

—Available on Windows 95™, Windows 98™ & Win-

dows NT™ for $99

—Supports all Cypress programmable logic products

Quantum38K™ ISR CPLD Family Members

[2]

Standby I_CC

Channel

memory

Speed — t_PD

Pin-to-Pin

(ns)

T_A=25°C

Maximum

I/O Pins

f_MAX2

(MHz)

Device

38K30

38K50

38K100

Typical Gates^[1]Macrocells

(Kbits)

3.3/2.5V

10 mA

16K–48K

23K–72K

46K–144K

512

768

176

218

302

125

1536

Note:

1. Upper limit of typical gates is calculated by assuming only 50% of the channel memory is used.

2. Standby I_CCvalues are with no output load and stable inputs.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-03043 Rev. *A

Revised July 5, 2001

12 3 4 5 6 7...32

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与CY38100V208B-125NI相关器件

型号	品牌	获取价格	描述	数据表
CY38100V208B-66NC	CYPRESS	获取价格	Loadable PLD, 18.9ns, CMOS, PQFP208, PLASTIC, QFP-208
CY38100V208B-66NI	CYPRESS	获取价格	Loadable PLD, 18.9ns, CMOS, PQFP208, PLASTIC, QFP-208
CY38100V208B-83NC	CYPRESS	获取价格	Loadable PLD, 15ns, CMOS, PQFP208, PLASTIC, QFP-208
CY38100V208B-83NI	CYPRESS	获取价格	Loadable PLD, 15ns, CMOS, PQFP208, PLASTIC, QFP-208
CY38100V256-125BBC	CYPRESS	获取价格	Loadable PLD, 10ns, 1536-Cell, CMOS, PBGA256, 17 X 17 MM, FBGA-256
CY38100V256-125BBI	CYPRESS	获取价格	Loadable PLD, 10ns, 1536-Cell, CMOS, PBGA256, 17 X 17 MM, FBGA-256
CY38100V256-66BBC	CYPRESS	获取价格	Loadable PLD, 18.9ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, TFBGA-256
CY38100V256-66BBI	CYPRESS	获取价格	Loadable PLD, 18.9ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, TFBGA-256
CY38100V256-83BBI	CYPRESS	获取价格	Loadable PLD, 15ns, 1536-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256
CY38100V256B-125BBC	CYPRESS	获取价格	Loadable PLD, 10ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256

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