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CY37512VP400-66BBI PDF预览

CY37512VP400-66BBI

更新时间： 2024-11-19 00:00:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
63页 1784K
描述
5V, 3.3V, ISR⑩ High-Performance CPLDs

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CY37512VP400-66BBI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：21 X 21 MM, 1.4 MM HEIGHT, 1.0 PITCH, FBGA-400
针数：400Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.8
其他特性：512 MACROCELLS最大时钟频率：50 MHz
系统内可编程：YESJESD-30 代码：S-PBGA-B400
JESD-609代码：e0JTAG BST：YES
长度：21 mm专用输入次数：1
I/O 线路数量：269宏单元数：512
端子数量：400最高工作温度：85 °C
最低工作温度：-40 °C组织：1 DEDICATED INPUTS, 269 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA400,20X20,40
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
可编程逻辑类型：EE PLD传播延迟：20 ns
认证状态：Not Qualified座面最大高度：1.4 mm
子类别：Programmable Logic Devices最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：21 mmBase Number Matches：1

CY37512VP400-66BBI 数据手册

 浏览型号CY37512VP400-66BBI的Datasheet PDF文件第2页浏览型号CY37512VP400-66BBI的Datasheet PDF文件第3页浏览型号CY37512VP400-66BBI的Datasheet PDF文件第4页浏览型号CY37512VP400-66BBI的Datasheet PDF文件第5页浏览型号CY37512VP400-66BBI的Datasheet PDF文件第6页浏览型号CY37512VP400-66BBI的Datasheet PDF文件第7页 
Ultra37000 CPLD Family  
5V, 3.3V, ISR™ High-Performance CPLDs  
Features  
General Description  
• In-System Reprogrammable™ (ISR™) CMOS CPLDs  
— JTAG interface for reconfigurability  
— Design changes do not cause pinout changes  
— Design changes do not cause timing changes  
• High density  
The Ultra37000™ family of CMOS CPLDs provides a range of  
high-density programmable logic solutions with unparalleled  
system performance. The Ultra37000 family is designed to  
bring the flexibility, ease of use, and performance of the 22V10  
to high-density CPLDs. The architecture is based on a number  
of logic blocks that are connected by a Programmable Inter-  
connect Matrix (PIM). Each logic block features its own  
product term array, product term allocator, and 16 macrocells.  
The PIM distributes signals from the logic block outputs and all  
input pins to the logic block inputs.  
— 32 to 512 macrocells  
— 32 to 264 I/O pins  
— Five dedicated inputs including four clock pins  
• Simple timing model  
All of the Ultra37000 devices are electrically erasable and In-  
System Reprogrammable (ISR), which simplifies both design  
and manufacturing flows, thereby reducing costs. The ISR  
feature provides the ability to reconfigure the devices without  
having design changes cause pinout or timing changes. The  
Cypress ISR function is implemented through a JTAG-  
compliant serial interface. Data is shifted in and out through  
the TDI and TDO pins, respectively. Because of the superior  
routability and simple timing model of the Ultra37000 devices,  
ISR allows users to change existing logic designs while simul-  
taneously fixing pinout assignments and maintaining system  
performance.  
— No fanout delays  
— No expander delays  
— No dedicated vs. I/O pin delays  
— No additional delay through PIM  
— No penalty for using full 16 product terms  
— No delay for steering or sharing product terms  
• 3.3V and 5V versions  
• PCI-compatible[1]  
• Programmable bus-hold capabilities on all I/Os  
• Intelligent product term allocator provides:  
— 0 to 16 product terms to any macrocell  
The entire family features JTAG for ISR and boundary scan,  
and is compatible with the PCI Local Bus specification,  
meeting the electrical and timing requirements. The  
Ultra37000 family features user programmable bus-hold  
capabilities on all I/Os.  
— Product term steering on an individual basis  
— Product term sharing among local macrocells  
• Flexible clocking  
Ultra37000 5.0V Devices  
The Ultra37000 devices operate with a 5V supply and can  
support 5V or 3.3V I/O levels. VCCO connections provide the  
capability of interfacing to either a 5V or 3.3V bus. By  
connecting the VCCO pins to 5V the user insures 5V TTL levels  
on the outputs. If VCCO is connected to 3.3V the output levels  
meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.  
These devices require 5V ISR programming.  
— Four synchronous clocks per device  
— Product term clocking  
— Clock polarity control per logic block  
• Consistent package/pinout offeringacrossall densities  
— Simplifies design migration  
— Same pinout for 3.3V and 5.0V devices  
• Packages  
Ultra37000V 3.3V Devices  
Devices operating with a 3.3V supply require 3.3V on all VCCO  
pins, reducing the device’s power consumption. These  
devices support 3.3V JEDEC standard CMOS output levels,  
and are 5V-tolerant. These devices allow 3.3V ISR  
programming.  
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,  
BGA, and Fine-Pitch BGA packages  
Note:  
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V.  
Cypress Semiconductor Corporation  
Document #: 38-03007 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised July 7, 2003  
1234567...63

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