Datasheet > CY37512P256-125BGC

CY37512P256-125BGC

更新时间： 2024-11-19 00:00:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
63页	1784K
描述
5V, 3.3V, ISR⑩ High-Performance CPLDs

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CY37512P256-125BGC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA-256
针数：	256	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.8
其他特性：	512 MACROCELLS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V	最大时钟频率：	83 MHz
系统内可编程：	YES	JESD-30 代码：	S-PBGA-B256
JESD-609代码：	e0	JTAG BST：	YES
长度：	27 mm	湿度敏感等级：	3
专用输入次数：	1	I/O 线路数量：	197
宏单元数：	512	端子数量：	256
最高工作温度：	70 °C	最低工作温度：
组织：	1 DEDICATED INPUTS, 197 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA256,20X20,50	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	220
电源：	3.3/5 V	可编程逻辑类型：	EE PLD
传播延迟：	10 ns	认证状态：	Not Qualified
座面最大高度：	2.46 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	27 mm
Base Number Matches：	1

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Ultra37000 CPLD Family

5V, 3.3V, ISR™ High-Performance CPLDs

Features

General Description

• In-System Reprogrammable™ (ISR™) CMOS CPLDs

— JTAG interface for reconfigurability

— Design changes do not cause pinout changes

— Design changes do not cause timing changes

• High density

The Ultra37000™ family of CMOS CPLDs provides a range of

high-density programmable logic solutions with unparalleled

system performance. The Ultra37000 family is designed to

bring the flexibility, ease of use, and performance of the 22V10

to high-density CPLDs. The architecture is based on a number

of logic blocks that are connected by a Programmable Inter-

connect Matrix (PIM). Each logic block features its own

product term array, product term allocator, and 16 macrocells.

The PIM distributes signals from the logic block outputs and all

input pins to the logic block inputs.

— 32 to 512 macrocells

— 32 to 264 I/O pins

— Five dedicated inputs including four clock pins

• Simple timing model

All of the Ultra37000 devices are electrically erasable and In-

System Reprogrammable (ISR), which simplifies both design

and manufacturing flows, thereby reducing costs. The ISR

feature provides the ability to reconfigure the devices without

having design changes cause pinout or timing changes. The

Cypress ISR function is implemented through a JTAG-

compliant serial interface. Data is shifted in and out through

the TDI and TDO pins, respectively. Because of the superior

routability and simple timing model of the Ultra37000 devices,

ISR allows users to change existing logic designs while simul-

taneously fixing pinout assignments and maintaining system

performance.

— No fanout delays

— No expander delays

— No dedicated vs. I/O pin delays

— No additional delay through PIM

— No penalty for using full 16 product terms

— No delay for steering or sharing product terms

• 3.3V and 5V versions

• PCI-compatible^[1]

• Programmable bus-hold capabilities on all I/Os

• Intelligent product term allocator provides:

— 0 to 16 product terms to any macrocell

The entire family features JTAG for ISR and boundary scan,

and is compatible with the PCI Local Bus specification,

meeting the electrical and timing requirements. The

Ultra37000 family features user programmable bus-hold

capabilities on all I/Os.

— Product term steering on an individual basis

— Product term sharing among local macrocells

• Flexible clocking

Ultra37000 5.0V Devices

The Ultra37000 devices operate with a 5V supply and can

support 5V or 3.3V I/O levels. V_CCOconnections provide the

capability of interfacing to either a 5V or 3.3V bus. By

connecting the V_CCOpins to 5V the user insures 5V TTL levels

on the outputs. If V_CCOis connected to 3.3V the output levels

meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.

These devices require 5V ISR programming.

— Four synchronous clocks per device

— Product term clocking

— Clock polarity control per logic block

• Consistent package/pinout offeringacrossall densities

— Simplifies design migration

— Same pinout for 3.3V and 5.0V devices

• Packages

Ultra37000V 3.3V Devices

Devices operating with a 3.3V supply require 3.3V on all V_CCO

pins, reducing the device’s power consumption. These

devices support 3.3V JEDEC standard CMOS output levels,

and are 5V-tolerant. These devices allow 3.3V ISR

programming.

— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,

BGA, and Fine-Pitch BGA packages

Note:

1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V_CC, PCI V_IH= 2V.

Cypress Semiconductor Corporation

Document #: 38-03007 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 7, 2003

12 3 4 5 6 7...63

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与CY37512P256-125BGC相关器件

型号	品牌	获取价格	描述	数据表
CY37512P256-154BGC	CYPRESS	获取价格	EE PLD, 7.5ns, 512-Cell, CMOS, PBGA256, 27 X 27 MM, 2.33 MM HEIGHT, BGA-256
CY37512P256-66BGC	CYPRESS	获取价格	EE PLD, 20ns, 512-Cell, CMOS, PBGA256, 27 X 27 MM, 2.33 MM HEIGHT, BGA-256
CY37512P256-66BGI	CYPRESS	获取价格	EE PLD, 20ns, 512-Cell, CMOS, PBGA256, 27 X 27 MM, 2.33 MM HEIGHT, BGA-256
CY37512P256-83BGC	CYPRESS	获取价格	5V, 3.3V, ISR⑩ High-Performance CPLDs
CY37512P256-83BGI	CYPRESS	获取价格	5V, 3.3V, ISR⑩ High-Performance CPLDs
CY37512P352-100BGC	CYPRESS	获取价格	5V, 3.3V, ISR⑩ High-Performance CPLDs
CY37512P352-100BGI	CYPRESS	获取价格	5V, 3.3V, ISR⑩ High-Performance CPLDs
CY37512P352-125BGC	CYPRESS	获取价格	5V, 3.3V, ISR⑩ High-Performance CPLDs
CY37512P352-125BGI	CYPRESS	获取价格	EE PLD, 10ns, 512-Cell, CMOS, PBGA352, BGA-352
CY37512P352-143BGC	CYPRESS	获取价格	EE PLD, 8.5ns, 512-Cell, CMOS, PBGA352, BGA-352

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