Datasheet > CY37512P208-100NTI

CY37512P208-100NTI

更新时间： 2025-07-18 19:43:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟输入元件可编程逻辑
页数	文件大小	规格书
65页	1184K
描述
EE PLD, 12ns, 512-Cell, CMOS, PQFP208, THERMALLY ENHANCED, PLASTIC, QFP-208

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CY37512P208-100NTI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	THERMALLY ENHANCED, PLASTIC, QFP-208
针数：	208	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.84
其他特性：	512 MACROCELLS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V	最大时钟频率：	80 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQFP-G208
JESD-609代码：	e0	JTAG BST：	YES
长度：	28 mm	湿度敏感等级：	3
专用输入次数：	1	I/O 线路数量：	160
宏单元数：	512	端子数量：	208
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	1 DEDICATED INPUTS, 160 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装等效代码：	QFP208,1.2SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3/5,5 V	可编程逻辑类型：	EE PLD
传播延迟：	12 ns	认证状态：	Not Qualified
座面最大高度：	3.77 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	28 mm
Base Number Matches：	1

CY37512P208-100NTI 数据手册

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Family

Ultra37000™ CPLD Family^[1]

5V, 3.3V, ISR™ High-Performance CPLDs

Features

General Description

• In-System Reprogrammable™ (ISR™) CMOS CPLDs

— JTAG interface for reconfigurability

— Design changes don’t cause pinout changes

— Design changes don’t cause timing changes

• High density

The Ultra37000™ family of CMOS CPLDs provides a range of

high-density programmable logic solutions with unparalleled

system performance. The Ultra37000 family is designed to

bring the flexibility, ease of use, and performance of the 22V10

to high-density CPLDs. The architecture is based on a number

of logic blocks that are connected by a Programmable Inter-

connect Matrix (PIM). Each logic block features its own prod-

uct term array, product term allocator, and 16 macrocells. The

PIM distributes signals from the logic block outputs and all in-

put pins to the logic block inputs.

— 32 to 512 macrocells

— 32 to 264 I/O pins

— 5 dedicated inputs including 4 clock pins

• Simple timing model

All of the Ultra37000 devices are electrically erasable and In-

System Reprogrammable (ISR), which simplifies both design

and manufacturing flows, thereby reducing costs. The ISR fea-

ture provides the ability to reconfigure the devices without hav-

ing design changes cause pinout or timing changes. The

Cypress ISR function is implemented through a JTAG-compli-

ant serial interface. Data is shifted in and out through the TDI

and TDO pins, respectively. Because of the superior routability

and simple timing model of the Ultra37000 devices, ISR allows

users to change existing logic designs while simultaneously

fixing pinout assignments and maintaining system perfor-

mance.

— No fanout delays

— No expander delays

— No dedicated vs. I/O pin delays

— No additional delay through PIM

— No penalty for using full 16 product terms

— No delay for steering or sharing product terms

• 3.3V and 5V versions

[2]

• PCI Compatible

• Programmable Bus-Hold capabilities on all I/Os

• Intelligent product term allocator provides:

— 0 to 16 product terms to any macrocell

The entire family features JTAG for ISR and boundary scan,

and is compatible with the PCI Local Bus specification, meet-

ing the electrical and timing requirements. The Ultra37000

family features user programmable bus-hold capabilities on all

I/Os.

— Product term steering on an individual basis

— Product term sharing among local macrocells

• Flexible clocking

Ultra37000 5.0V Devices

The Ultra37000 devices operate with a 5V supply and can sup-

— 4 synchronous clocks per device

— Product Term clocking

port 5V or 3.3V I/O levels. V

connections provide the ca-

CCO

pability of interfacing to either a 5V or 3.3V bus. By connecting

the V pins to 5V the user insures 5V TTL levels on the

CCO

outputs. If V

— Clock polarity control per logic block

• Consistent package/pinout offering across all densities

— Simplifies design migration

is connected to 3.3V the output levels meet

CCO

3.3V JEDEC standard CMOS levels and are 5V tolerant.

These devices require 5V ISR programming.

— Same pinout for 3.3V and 5.0V devices

• Packages

Ultra37000V 3.3V Devices

Devices operating with a 3.3V supply require 3.3V on all V

CCO

— 44 to 400 Leads in PLCC, CLCC, PQFP, TQFP, CQFP,

BGA, and Fine-Pitch BGA packages

pins, reducing the device’s power consumption. These devices

support 3.3V JEDEC standard CMOS output levels, and are

5V tolerant. These devices allow 3.3V ISR programming.

Notes:

1. The data sheet parameters are final for the following devices: CY37032, CY37032V (with the exception of the 154-MHz speed bin), CY37128, CY37128V (with

the exception of the 154-MHz speed bin), CY37192, CY37192V, CY37256, and CY37256V (with the exception of the 143-MHz speed bin). The data sheet

parameters are considered preliminary for the following devices: CY37064, CY37064V, CY37384, CY37384V, CY37512, and CY37512V.

2. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V_CC, PCI V_IH=2V.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

February 9, 2000

12 3 4 5 6 7...65

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与CY37512P208-100NTI相关器件

型号	品牌	获取价格	描述	数据表
CY37512P208-100UM	CYPRESS	获取价格	5V, 3.3V, ISRTM High-Performance CPLDs
CY37512P208-100UMB	CYPRESS	获取价格	EE PLD, 12ns, 512-Cell, CMOS, CQFP208, CAVITY UP, CERAMIC, QFP-208
CY37512P208-125NC	CYPRESS	获取价格	5V, 3.3V, ISR⑩ High-Performance CPLDs
CY37512P208-125NI	CYPRESS	获取价格	EE PLD, 10ns, 512-Cell, CMOS, PQFP208, PLASTIC, QFP-208
CY37512P208-143NC	CYPRESS	获取价格	EE PLD, 8.5ns, 512-Cell, CMOS, PQFP208, PLASTIC, QFP-208
CY37512P208-154NC	CYPRESS	获取价格	EE PLD, 7.5ns, 512-Cell, CMOS, PQFP208, PLASTIC, QFP-208
CY37512P208-66NC	CYPRESS	获取价格	EE PLD, 20ns, 512-Cell, CMOS, PQFP208, PLASTIC, QFP-208
CY37512P208-83NC	CYPRESS	获取价格	5V, 3.3V, ISR⑩ High-Performance CPLDs
CY37512P208-83NI	CYPRESS	获取价格	5V, 3.3V, ISR⑩ High-Performance CPLDs
CY37512P256-100BGC	CYPRESS	获取价格	5V, 3.3V, ISR⑩ High-Performance CPLDs

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