CY3138
Warp Enterprise™ Verilog CPLD Software
• VHDL or Verilog timing model output for use with
third-party simulators
Features
• Verilog (IEEE 1364) high-level language compilers
with the following features:
• Active-HDL™ Sim Release 4.1 timing simulation from
Aldec
— Designs are portable across multiple devices
and/or EDA environments
— Graphical waveform simulator
— Graphical entry and modification of all waveforms
— Facilitates the use of industry-standard simulation
and synthesis tools for board- and system-level de-
sign
— Ability to compare waveforms and highlight differ-
ences before and after a design change
— Ability to probe internal nodes
— Support for functions and libraries facilitating mod-
ular design methodology
— Display of inputs, outputs, and high impedance (Z)
signals in different colors
— Support for reduction and conditional operators,
blockingandnon-blockingproceduralassignments,
while loops and integers
— Automatic clock and pulse creation
— Support for buses
• Several design entry methods support high-level and
low-level design descriptions:
— Unlimited simulation time
— Graphical HDL Block Diagram editor with a library of
blocks and a text-to-block conversion utility from Al-
dec
• Architecture Explorer™ analysis tool and Dynamic
Timing Simulator for PSI and Delta39K devices:
— Graphicalrepresentationofexactlyhowyourdesign
will be implemented on your specific target device
— Aldec Active-HDL™ FSM graphical Finite State
Machine editor
— Zoom from the device level down to the macrocell
level
— Behavioral Verilog (IF...THEN...ELSE; CASE...)
— Boolean
— Determine the timing for any path and view that path
on a graphical representation of the chip
— Structural Verilog
• Static Timing Report for all devices
— Designs can include multiple entry methods (but
only one HDL) in a single design.
• Source-Level Behavioral Simulation and Debugger
from Aldec
• Language Assistant library of Verilog templates
• Testbench Generation
• Flow Manager Interface to keep track of complex
projects
• C3ISR Programming Cable
• UltraGen™ Synthesis and Fitting Technology:
• Delta39K\Ultra37000 prototype board with a
CY37256V 160-pin TQFP device and a CY39100V
208-pin device
— Infers“modules” such as adders, comparators, etc.,
frombehavioraldescriptionsandreplacesthemwith
circuits pre-optimized for the target device.
• On-line documentation and help
— User-selectable speed and/or area optimization on a
block-by-block basis
Functional Description
— Perfectly integrated synthesis and fitting
Warp Enterprise™ is an integration of the Warp Profes-
sional™ CPLD Development package with additional sophis-
ticated EDA software features from Aldec. In addition to
accepting IEEE 1364 Verilog text and graphical finite state
machines for design entry, Warp Enterprise Verilog provides a
graphical HDL block diagram editor with a library of graphical
HDL blocks pre-optimized for Cypress devices. Plus, it
provides a utility to convert HDL text into graphical HDL blocks.
Warp Enterprise synthesizes and optimizes the entered
design, and outputs a JEDEC or Intel® hex file for the desired
PLD or CPLD (see Figure 1). For simulation, Warp Enterprise
provides a timing simulator, a source-level behavioral
simulator, as well as VHDL and Verilog timing models for use
with third party simulators. Warp Enterprise also provides the
designer with important productivity tools such as a testbench
generation wizard and the Architecture Explorer graphical
analysis tool.
— Automatic selection of optimal flip-flop type
(D type/T type)
— Automatic pin assignment
• Ability to specify timing constraints for all of the
Delta39K and PSI devices
• Support for all Cypress Programmable Logic Devices
— PSI™ (Programmable Serial Interface)
— Delta39K™ CPLDs
— Ultra37000™ CPLDs
— FLASH370i™ CPLDs
— MAX340™ CPLDs
— Industry standard PLDs (16V8, 20V8, 22V10)
Cypress Semiconductor Corporation
Document #: 38-03045 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised August 19, 2003
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