8
CY3128
Warp Professional™ CPLD Software
• Support for all Cypress Programmable Logic Devices
—PSI™ (Programmable Serial Interface™)
Features
• VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)
high-level language compilers with the following fea-
tures:
— Designs are portable across multiple devices
and/or EDA environments
—Delta39K™ CPLDs
—Quantum38K™ CPLDs
—Ultra37000™ CPLDs
—FLASH370i™ CPLDs
— Facilitates the use of industry-standard simulation
and synthesis tools for board- and system-level
design
—MAX340™ CPLDs
—Industry standard PLDs (16V8, 20V8, 22V10)
— Support for functions and libraries facilitating
modular design methodology
• VHDL and Verilog timing model output for use with
third-party simulators
• IEEE Standard 1076 and 1164 VHDL synthesis
supports:
• Active-HDL™ Sim Release 4.1 timing simulation from
Aldec
— Enumerated types
—Graphical waveform simulator
— Operator overloading
—Graphical entry and modification of stimulus wave-
forms
— For... Generate statements
— Integers
—Ability to compare waveforms and highlight differ-
ences before and after a design change
• IEEE Standard 1364 Verilog synthesis supports:
— Reduction and conditional operators
— Blocking and non-blocking procedural assignments
— While loops
—Ability to probe internal nodes
—Display of inputs, outputs, and high impedance (Z)
signals in different colors
—Automatic clock and pulse creation
—Support for buses
— Integers
• Several design entry methods support high-level and
low-level design descriptions:
—Up to 5 ms simulation time
• Architecture Explorer analysis tool and Dynamic Tim-
ing Analysis for PSI, Delta39K and Quantum38K devic-
es:
— Graphical HDL Block Diagram editor and a library of
blocks from Aldec
— Aldec Active-HDL™ FSM graphical Finite State
Machine editor
—Graphicalrepresentationofexactlyhowyourdesign
will be implemented on your specific target device
— Behavioral VHDL and Verilog (IF...THEN...ELSE;
CASE...)
—Zoom from the device level down to the macrocell
level
— Boolean
—Determine the timing for any path and view that path
— Structural Verilog and VHDL
on a graphical representation of the chip
— Designs can include multiple entry methods (but
only one HDL) in a single design.
• Static Timing Report for all devices
• UltraISR Programming Cable
• Language Assistant library of VHDL and Verilog tem-
plates
• Flow Manager Interface to keep track of complex
projects
• Delta39K\Ultra37000 prototype board with a CY37256V
160-pin TQFP device and a CY39100V 208-pin PQFP
device[1]
• On-line documentation and help
• UltraGen™ Synthesis and Fitting Technology:
Functional Description
— Infers“modules” such as adders, comparators, etc.,
frombehavioraldescriptionsandreplacesthemwith
circuits pre-optimized for the target device.
Warp Professional™ is an integration of the Warp® CPLD De-
velopment package with additional sophisticated EDA soft-
ware features from Aldec. In addition to accepting IEEE
1076/1164 VHDL text, IEEE 1364 Verilog text and graphical
finite state machines for design entry, Warp Professional pro-
vides a graphical HDL block diagram editor with a library of
graphical HDL blocks pre-optimized for Cypress devices. It
synthesizes and optimizes the entered design, and outputs a
JEDEC or Intel hex file for the desired PLD or CPLD (see Fig-
ure 1). For simulation, Warp Professional provides a timing
simulator, as well as VHDL timing models for use with third
party simulators. Warp Professional also provides the design-
er with important productivity tools like the Architecture Explor-
er graphical analysis tool.
— User-selectable speed and/or area optimization on a
block-by-block basis
— Perfectly integrated synthesis and fitting
— Automatic selection of optimal flip-flop type
(D type/T type)
— Automatic pin assignment
Note:
1. Cypress reserves the right to substitute prototype boards based on availability.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03047 Rev. *A
Revised January 9, 2002
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