Datasheet > CY3125R62

CY3125R62

更新时间： 2024-09-09 23:44:59

品牌	Logo	应用领域
其他 - ETC		可编程逻辑
页数	文件大小	规格书
8页	86K
描述
Programmable Logic

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中文翻译

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数据手册

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CY3125R62 数据手册

CY3125

Warp^®CPLD Development Tool for UNIX

—Industry-standard PLDs (16V8, 20V8, 22V10)

Features

• VHDL and Verilog timing model output for use with

third-party simulators

• Static Timing Report:

• VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)

high-level language compilers with the following

features:

— Designs are portable across multiple devices

and/or EDA environments

—Provides timing information for any path broken

down by the different steps of the path

— Facilitates the use of industry-standard simulation

and synthesis tools for board and system-level

design

• ArchitectureExplorerandDynamicTimingAnalysisfor

PSI, Delta39K and Quantum38K devices:

—Graphicalrepresentationofexactlyhowyourdesign

will be implemented on your specific target device

— Support for functions and libraries facilitating

modular design methodology

—Zoom from the device level down to the macrocell

level

• IEEE Standard 1076 and 1164 VHDL synthesis

supports:

—Determine the timing for any path and view that path

— Enumerated types

on a graphical representation of the chip

— Operator overloading

• Workstation support for Sun Solaris™

• On-line documentation and help

— For... Generate statements

— Integers

Functional Description

• IEEE Standard 1364 Verilog synthesis supports:

— Reduction and conditional operators

— Blocking and non-blocking procedural assignments

— While loops

VHDL

Verilog

State Machine

— Integers

• Several design entry methods support high-level and

low-level design descriptions:

— Behavioral VHDL and Verilog (IF...THEN...ELSE;

CASE...)

— Boolean

UltraGen^TM

Synthesis

and

— Structural Verilog and VHDL

— Designs can include multiple entry methods (but

Fitting

only one HDL language) in a single design.

• UltraGen™ Synthesis and Fitting Technology:

— Infers“modules”such as adders, comparators, etc.,

frombehavioraldescriptionsandreplacesthemwith

circuits pre-optimized for the target device.

— User-selectable speed and/or area optimization on a

block-by-block basis

— Perfect communication between synthesis and fit-

VHDL, Verilog

Programming

File

Timing

Simulator

&Third-Party

ting

Simulation Models

— Automatic selection of optimal flip-flop type

(D type/T type)

Figure 1. Warp^®VHDL Design Flow

— Automatic pin assignment

Warp^®is a state-of-the-art HDL compiler for designing with

Cypress’s Complex Programmable Logic Devices (CPLDs).

Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE

1364 Verilog as its Hardware Description Languages (HDL) for

design entry. Then, it synthesizes and optimizes the entered

design, and outputs a JEDEC or Intel hex file for the desired

PLD or CPLD (see Figure 1). Furthermore, Warp accepts

VHDL or Verilog produced by the Active-HDL FSM graphical

Finite State Machine editor. For simulation, Warp provides a

timing simulator, as well as VHDL and Verilog timing models

for use with third party simulators.

• Supports for the following Cypress Programmable

Logic Devices:

— PSI™ (Programmable Serial Interface™)

— Delta39K™ CPLDs

— Quantum38K™ CPLDs

— Ultra37000™ CPLDs

— FLASH370i™ CPLDs

— MAX340™ CPLDs

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-03046 Rev. *A

Revised January 9, 2002

12 3 4 5 6 7 8

中文翻译

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与CY3125R62相关器件

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CY3128	CYPRESS	获取价格	Warp Professional CPLD Software
CY3128R62	CYPRESS	获取价格	Warp Professional CPLD Software
CY3130	CYPRESS	获取价格	Warp Enterprise⑩ VHDL CPLD Software
CY3130R62	CYPRESS	获取价格	Warp Enterprise⑩ VHDL CPLD Software
CY3138	CYPRESS	获取价格	Warp Enterprise⑩ Verilog CPLD Software
CY3138R62	CYPRESS	获取价格	Warp Enterprise⑩ Verilog CPLD Software
CY3207ISSP	CYPRESS	获取价格	In-System Serial Programming (ISSP) Guide
CY3217	CYPRESS	获取价格	PSoC MiniProg
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CY325B	ETC	获取价格	LCD Controller

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