Datasheet > CY3120R62

CY3120R62

更新时间： 2024-09-10 09:41:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		PC
页数	文件大小	规格书
8页	71K
描述
Warp-R CPLD Development Software for PC

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中文翻译

获取价格

数据手册

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CY3120R62 数据手册

CY3120

Warp CPLD Development Software for PC

— Perfect communication between synthesis and

fitting

Features

• VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)

high-level language compilers with the following

features

— Automatic selection of optimal flip-flop type

(D type/T type)

— Automatic pin assignment

— Designs are portable across multiple devices

and/or EDA environments

• Ability to specify timing constraints for all of the

Delta39K and PSI devices

• Supports all Cypress Programmable Logic Devices

— PSI™ (Programmable Serial Interface)

— Facilitates the use of industry-standard simulation

and synthesis tools for board and system-level

design

— Support for functions and libraries facilitating

modular design methodology

— Delta39K™ Complex Programmable Logic Devices

(CPLDs)

• IEEE Standard 1076 and 1164 VHDL synthesis supports

— Enumerated types

— Ultra37000™ CPLDs

— FLASH370i™ CPLDs

— Operator overloading

— MAX340™ CPLDs

— For... Generate statements

— Integers

— Industry standard PLDs (16V8, 20V8, 22V10)

• VHDL and Verilog timing model output for use with

third-party simulators

• Timing simulation provided by Active-HDL™ Sim

Release 3.3 from Aldec

• IEEE Standard 1364 Verilog synthesis supports

— Reduction and conditional operators

— Blocking and non-blocking procedural assignments

— While loops

— Graphical waveform simulator

— Entry and modification of on-screen waveforms

— Ability to probe internal nodes

— Integers

• Several design entry methods support high-level and

low-level design descriptions

— Display of inputs, outputs, and high impedance (Z)

signals in different colors

— Behavioral VHDL and Verilog (IF...THEN...ELSE;

CASE...)

— Automatic clock and pulse creation

— Support for buses

— Boolean

• ArchitectureExplorerandDynamicTimingAnalysisfor

PSI and Delta39K devices

— Aldec Active-HDL™ FSM graphical Finite State

Machine editor

— Graphicalrepresentationofexactlyhowyourdesign

will be implemented on your specific target device

— Structural Verilog and VHDL

— Designs can include multiple entry methods (but

only one HDL language) in a single design

— Zoom from the device level down to the macrocell

level

• UltraGen™ Synthesis and Fitting Technology

— Determine the timing for any path and view that path

on a graphical representation of the chip

— Infers“modules” such as adders, comparators, etc.,

frombehavioraldescriptionsandreplacesthemwith

circuits pre-optimized for the target device

• Static Timing Report for all devices

• PC Support (Windows 98™, Windows NT™ 4.0, and

Windows XP™)

— User selectable speed and/or area optimization on a

block-by-block basis

• On-line documentation and help

Cypress Semiconductor Corporation

Document #: 38-03049 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 18, 2002

12 3 4 5 6 7 8

中文翻译

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与CY3120R62相关器件

型号	品牌	获取价格	描述	数据表
CY3125	CYPRESS	获取价格	Warp CPLD Development Tool for UNIX
CY3125R62	ETC	获取价格	Programmable Logic
CY3128	CYPRESS	获取价格	Warp Professional CPLD Software
CY3128R62	CYPRESS	获取价格	Warp Professional CPLD Software
CY3130	CYPRESS	获取价格	Warp Enterprise⑩ VHDL CPLD Software
CY3130R62	CYPRESS	获取价格	Warp Enterprise⑩ VHDL CPLD Software
CY3138	CYPRESS	获取价格	Warp Enterprise⑩ Verilog CPLD Software
CY3138R62	CYPRESS	获取价格	Warp Enterprise⑩ Verilog CPLD Software
CY3207ISSP	CYPRESS	获取价格	In-System Serial Programming (ISSP) Guide
CY3217	CYPRESS	获取价格	PSoC MiniProg

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