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CY2XP21ZXC

更新时间： 2024-11-26 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
7页	224K
描述
125 MHz LVPECL Clock Generator

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中文翻译

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数据手册

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CY2XP21ZXC 数据手册

PRELIMINARY

CY2XP21

125 MHz LVPECL Clock Generator

Features

Functional Description

■

One LVPECL Output Pair

The CY2XP21 is a PLL (Phase Locked Loop) based high

performance clock generator. It is optimized to generate a

125 MHz clock, which is ideal for 10 Gb Ethernet applications. It

also produces an output frequency that is five times the crystal

frequency. It uses Cypress’s low noise VCO technology to

achieve less than 1 ps typical RMS phase jitter. The CY2XP21

has a crystal oscillator interface input and one LVPECL output

pair.

Output Frequency: 112 MHz to 140 MHz

External Crystal Frequency: 22.4 MHz to 28 MHz

Low RMS Phase Jitter at 125 MHz, using 25 MHz Crystal

(1.875 MHz to 20 MHz): 0.4 ps (Typical)

■

Pb-free 8-Pin TSSOP Package

Supply Voltage: 3.3V or 2.5V

Commercial and Industrial Temperature Ranges

Logic Block Diagram

XIN

External

Crystal

CLK

CRYSTAL

OSCILLATOR

LOW -N OISE

PLL

OUTPUT

DIVIDER

CLK#

XOUT

Pinouts

Figure 1. Pin Diagram - 8-Pin TSSOP

VDD

VSS

XOUT

XIN

VDD

CLK

CLK#

Table 1. Pin Definition - 8-Pin TSSOP

Pin Number

Pin Name

VDD

I/O Type

Description

1, 8

Power

3.3V or 2.5V power supply

Ground

VSS

3, 4

XOUT, XIN

XTAL output and input

Parallel resonant crystal interface

No Connect

6,7

CLK#, CLK

LVPECL output

Differential Clock Output

Cypress Semiconductor Corporation

Document #: 001-52849 Rev. *A

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised June 15, 2009

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