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CY2SSTV855ZCT

更新时间: 2024-02-05 02:09:34
品牌 Logo 应用领域
SPECTRALINEAR 驱动器逻辑集成电路电视光电二极管时钟
页数 文件大小 规格书
6页 93K
描述
Differential Clock Buffer/Driver

CY2SSTV855ZCT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.13Is Samacsys:N
系列:SSTV输入调节:MUX
JESD-30 代码:R-PDSO-G28长度:9.7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:28
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):6 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.1 ns
座面最大高度:1.1 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm最小 fmax:60 MHz
Base Number Matches:1

CY2SSTV855ZCT 数据手册

 浏览型号CY2SSTV855ZCT的Datasheet PDF文件第2页浏览型号CY2SSTV855ZCT的Datasheet PDF文件第3页浏览型号CY2SSTV855ZCT的Datasheet PDF文件第4页浏览型号CY2SSTV855ZCT的Datasheet PDF文件第5页浏览型号CY2SSTV855ZCT的Datasheet PDF文件第6页 
CY2SSTV855  
Differential Clock Buffer/Driver  
Functional Description  
Features  
• Phase-locked loop (PLL) clock distribution for Double  
Data Rate Synchronous DRAM applications  
The CY2SSTV855 is a high-performance, very-low-skew,  
very-low-jitter zero-delay buffer that distributes a differential  
clock input pair (SSTL_2) to four differential (SSTL_2) pairs of  
clock outputs and one differential pair of feedback clock  
outputs. In support of low power requirements, when  
power-down is HIGH, the outputs switch in phase and  
frequency with the input clock. When power-down is LOW, all  
outputs are disabled to a high-impedance state and the PLL is  
shut down.  
• 1:5 differential outputs  
• External feedback pins (FBINT, FBINC) are used to  
synchronize the outputs to the clock input  
• SSCG: Spread Aware™ for electromagnetic  
interference (EMI) reduction  
• 28-pin TSSOP package  
The device supports a low-frequency power-down mode.  
When the input is < 20 MHz, the PLL is disabled and the  
outputs are put in the Hi-Z state. When the input frequency is  
> 20 MHz, the PLL and outputs are enabled.  
• Conforms to JEDEC DDR specifications  
When AVDD is tied to ground, the PLL is turned off and  
bypassed with the input reference clock gated to the outputs.  
The Cypress CY2SSTV855 is Spread Aware and supports  
tracking of Spread Spectrum clock inputs to reduce EMI  
Pin Configuration  
Block Diagram  
GND  
GND  
YC0  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
YT0  
YC0  
YC3  
2
PWRDWN  
AVDD  
Powerdown  
and test  
logic  
YT3  
YT0  
3
VDDQ  
GND  
VDDQ  
PWRDWN  
FBINT  
FBINC  
VDDQ  
FBOUTC  
FBOUTT  
VDDQ  
YT2  
4
YT1  
YC1  
5
CLKINT  
CLKINC  
VDDQ  
AVDD  
AGND  
6
7
8
YT2  
YC2  
9
CLKINT  
CLKINC  
10  
11  
12  
13  
14  
PLL  
YT3  
YC3  
FBINT  
FBINC  
VDDQ  
YT1  
YC2  
YC1  
FBOUTT  
FBOUTC  
GND  
GND  
28-pin TSSOP  
Rev 1.0, November 21, 2006  
Page 1 of 6  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  

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