Datasheet > CY2SSTV16857

CY2SSTV16857

更新时间： 2024-11-24 04:13:23

品牌	Logo	应用领域
SPECTRALINEAR		PC
页数	文件大小	规格书
7页	91K
描述
14-Bit Regstered Buffer PC2700-/PC3200-Compliant

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CY2SSTV16857 数据手册

CY2SSTV16857

14-Bit Registered Buffer PC2700-/PC3200-Compliant

When RESET is LOW, the differential input receivers are

disabled, and undriven (floating) data, clock, and REF voltage

Features

• Differential Clock Inputs up to 280 MHz

inputs are allowed. In addition, when RESET is LOW, all

registers are reset and all outputs force to the LOW state. The

LVCMOS RESET input must always be held at a valid logic

HIGH or LOW level.

• Supports LVTTL switching levels on the RESET pin

• Output drivers have controlled edge rates, so no

external resistors are required

To ensure defined outputs from the register before a stable

clock has been supplied, RESET must be held in the LOW

state during power-up.

• Two KV ESD protection

• Latch-upperformanceexceeds 100 mA: JESD78, Class II

In the DDR registered DIMM application, RESET is specified

to be completely asynchronous with respect to CLK and CLK.

Therefore, no timing relationship can be guaranteed between

the two. When entering reset, the register will be cleared and

the outputs will be driven LOW quickly, relative to the time to

disable the differential input receivers, thus ensuring no

glitches on the output. However, when coming out of reset, the

enable the differential input receivers. As long as the data

inputs are low, and the clock is stable during the time from the

LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design must ensure that the outputs will

remain LOW.

• Conforms to JEDEC STD (JESD82-3) for buffered DDR

DIMMs

• 48-pin TSSOP

Description

This 14-bit registered buffer is designed specifically for 2.3V to

2.7V V_DDoperation and is characterized for operation from

0°C to + 85°C.

All inputs are compatible with the JEDEC Standard for

SSTL_2, except the LVCMOS reset (RESET) input. All outputs

are SSTL_2, Class II-compatible.

The SSTV16857 operates from a differential clock (CLK and

CLK). Data is measured at the crossing of CLK going HIGH,

and CLK going LOW.

Pin Configuration

Block Diagram

RESET

VSS

VDDQ

VSS

VDD

CLK

VSS

VDDQ

VREF

CLK

VDD

VSS

VREF

RESET

VDDQ

VSS

VDDQ

VSS

Q10

Q11

Q12

VDDQ

VSS

Q13

Q14

D10

D11

D12

VDD

VSS

D13

D14

To 13 Other Channels

Rev 1.0, November 21, 2006

Page 1 of 7

www.SpectraLinear.com

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555 Fax:(408) 855-0550

12 3 4 5 6 7

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与CY2SSTV16857相关器件

型号	品牌	获取价格	描述	数据表
CY2SSTV16857ZC	SPECTRALINEAR	获取价格	14-Bit Regstered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZC	CYPRESS	获取价格	14-Bit Registered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZCT	SPECTRALINEAR	获取价格	14-Bit Regstered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZCT	CYPRESS	获取价格	14-Bit Registered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZI	SPECTRALINEAR	获取价格	14-Bit Regstered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZI	CYPRESS	获取价格	14-Bit Registered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZIT	SPECTRALINEAR	获取价格	14-Bit Regstered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZIT	CYPRESS	获取价格	14-Bit Registered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZIT	SILICON	获取价格	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, 0.
CY2SSTV16857ZXC	CYPRESS	获取价格	14-Bit Registered Buffer PC2700-/PC3200-Compliant

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