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CY2CC1810O PDF预览

CY2CC1810O

更新时间: 2024-10-01 08:22:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管
页数 文件大小 规格书
11页 93K
描述
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, SSOP-24

CY2CC1810O 数据手册

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Preliminary  
CY2CC1810  
1:10 Signal Fanout Buffer w/ Output Enable  
ComLTM SERIES  
Product Features  
Product Description  
The CYPRESS ComL series of network circuits are  
produced using advanced 0.35 micron CMOS  
technology, achieving the industries fastest logic and  
buffers.  
Low Voltage Operation  
VDD range from 3.6 to 1.65V  
1:10 Fanout  
Low input capacitance  
Low output skew  
Low propagation delay  
High Speed (tpd<5.0ns)  
The CYPRESS CY2CC1810 fanout buffer features  
one input and ten outputs.  
Designed  
for  
Data  
Communications  
clock  
High Speed Operation >200MHz  
management applications, the large fanout from a  
single input reduces loading on the input clock.  
LVTTL/LVCMOS compatible input  
Output Disable to Tri-state  
VOI ä Output Drivers for low noise  
AVCMOS type outputs dynamically adjust for variable  
impedance matching and eliminate the need for series  
damping resistors and reduce noise overall.  
Eliminates the need for series damping resistors  
Industrial Operation at 0°C to +85°C  
Packages available include: SOIC/SSOP  
Pin Configuration  
Block Diagram  
23  
21  
5
Q1  
GND  
Q10  
VDD  
Q9  
GND  
Q1  
OE#  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
Q9  
Q10  
VDD  
Q2  
19  
18  
OE#  
IN  
GND  
GND  
Q3  
Q4  
VDD  
3,10  
15,22  
GND  
Q8  
GND  
Q5  
16  
14  
11  
9
9
6
VDD  
VDD  
Q6  
GND  
10  
11  
12  
Q7  
GND  
1,12,13  
17,24  
IN  
24 pin SOIC/SSOP  
GND  
4
2
OUTPUT (AVCMOS)  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07055 Rev. **  
5/8/2001  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 1 of 11  

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