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CY29FCT52TSOIC

更新时间： 2024-09-29 22:50:39
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
10页 263K
描述
8-Bit Registered Transceiver

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CY29FCT52TSOIC 数据手册

 浏览型号CY29FCT52TSOIC的Datasheet PDF文件第2页浏览型号CY29FCT52TSOIC的Datasheet PDF文件第3页浏览型号CY29FCT52TSOIC的Datasheet PDF文件第4页浏览型号CY29FCT52TSOIC的Datasheet PDF文件第5页浏览型号CY29FCT52TSOIC的Datasheet PDF文件第6页浏览型号CY29FCT52TSOIC的Datasheet PDF文件第7页 
CY29FCT52T  
8-BIT REGISTERED TRANSCEIVER  
SCCS010A – MAY 1994 – REVISED OCTOBER 2001  
Q OR SO PACKAGE  
(TOP VIEW)  
Function, Pinout, and Drive Compatible  
With FCT, F Logic, and AM2952  
Reduced V  
of Equivalent FCT Functions  
(Typically = 3.3 V) Versions  
B
B
B
B
B
B
B
B
V
A
A
A
A
A
A
A
A
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
OH  
7
6
5
4
3
2
1
0
CC  
7
2
3
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
6
4
5
5
4
6
3
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
7
2
8
1
OEB  
CPA  
CEA  
9
– 1000-V Charged-Device Model (C101)  
0
OEA  
CPB  
10  
11  
I
Supports Partial-Power-Down Mode  
off  
Operation  
GND 12  
13 CEB  
Matched Rise and Fall Times  
Fully Compatible With TTL Input and  
Output Logic Levels  
64-mA Output Sink Current  
32-mA Output Source Current  
description  
The CY29FCT52T has two 8-bit back-to-back registers that store data flowing in both directions between two  
bidirectional buses. Separate clock, clock enable, and 3-state output-enable signals are provided for each  
register. Both A outputs and B outputs are specified to sink 64 mA.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
PIN DESCRIPTION  
NAME  
DESCRIPTION  
A
B
A register inputs or B register outputs  
B register inputs or A register outputs  
CPA  
Clock for the A register. When CEA is low, data enters the A register on the low-to-high transition of the CPA signal.  
ClockenablefortheAregister.WhenCEAislow,dataenterstheAregisteronthelow-to-hightransitionoftheCPAsignal.WhenCEA  
is high, the A register holds its contents, regardless of CPA signal transitions.  
CEA  
OutputenablefortheAregister.WhenOEAislow,theAregisteroutputsareenabledontotheBlines.WhenOEAishigh,theAoutputs  
are in the high-impedance state.  
OEA  
CPB  
CEB  
Clock for the B register. When CEB is low, data enters the B register on the low-to-high transition of the CPB signal.  
Clock enable for the B register. When CEB is low, data enters the B register on the low-to-high transition of the CPB signal. When  
CEB is high, the B register holds its contents, regardless of CPA signal transitions.  
OutputenablefortheBregister.WhenOEBislow,theBregisteroutputsareenabledontotheAlines.WhenOEBishigh,theBoutputs  
are in the high-impedance state.  
OEB  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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