Datasheet > CY28410ZZCT

CY28410ZZCT

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
18页	283K
描述
Processor Specific Clock Generator, 400MHz, CMOS, PDSO56, 6 X 14 MM, LEAD FREE, TSSOP2-56

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CY28410ZZCT 数据手册

CY28410

Clock Generator for Intel^Grantsdale Chipset

• 33-MHz PCI clock

Features

• Low-voltage frequency select input

• Compliant with Intel^CK410

• I²C support with readback capabilities

• Supports Intel P4 and Tejas CPU

• Selectable CPU frequencies

• Differential CPU clock pairs

• 100-MHz differential SRC clocks

• 96-MHz differential dot clock

• 48-MHz USB clocks

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• 3.3V power supply

• 56-pin SSOP and TSSOP packages

CPU

SRC

PCI

x 9

REF

x 1

DOT96C

x 1

USB_48

x 1

x2 / x3

x6 / x7

Block Diagram

Pin Configuration

VDD_REF

REF

VDD_PCI

VSS_PCI

PCI3

PCI2

PCI1

PCI0

XIN

XTAL

OSC

XOUT

PLL Ref Freq

VDD_CPU

PCI4

FS_C/TEST_SEL

REF

CPUT[0:1], CPUC[0:1],

CPU(T/C)2_ITP]

VDD_SRC

Divider

PLL1

PCI5

Network

VSS_PCI

VDD_PCI

PCIF0/ITP_EN

PCIF1

VSS_REF

XIN

SRCT[1:6], SRCC[1:6]

FS_[C:A]

VTT_PWRGD#

XOUT

VDD_REF

SDATA

IREF

PCIF2

VDD_PCI

PCI[0:5]

VDD_PCIF

PCIF[0:2]

VDD_48

USB_48

VSS_48

DOT96T

DOT96C

SCLK

VSS_CPU

CPUT0

CPUC0

VDD_CPU

CPUT1

VDD_48 MHz

FS_B/TEST_MODE

VTT_PWRGD#/PD

FS_A

DOT96T

DOT96C

USB_48

CPUC1

PLL2

IREF

SRCT1

VSSA

SRCC1

VDDA

VDD_SRC

SRCT2

CPUT2_ITP/SRCT7

CPUC2_ITP/SRCC7

VDD_SRC

SRCT6

SRCC2

SRCT3

SRCC3

SRCC6

SRC4-SATAT

SRC4_SATAC

VDD_SRC

SRCT5

SDATA

SCLK

I C

Logic

SRCC5

VSS_SRC

56 SSOP/TSSOP

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07593 Rev. **

Revised December 22, 2003

12 3 4 5 6 7...18

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