Datasheet > CY28409_06

CY28409_06

更新时间： 2024-01-09 15:07:12

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
17页	346K
描述
Clock Synthesizer with Differential SRC and CPU Outputs

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中文翻译

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CY28409_06 数据手册

CY28409

Clock Synthesizer with Differential SRC and

CPU Outputs

• Three differential CPU clock pairs

Features

• One differential SRC clock

• I²C support with readback capabilities

• Supports Intel^®Pentium^®4-type CPUs

• Selectable CPU frequencies

• 3.3V power supply

• Ideal Lexmark Spread Spectrum profile for maximum

EMI reduction

• Ten copies of PCI clocks

• 56-pin SSOP and TSSOP packages

• Five copies of 3V66 with one optional VCH

• Two copies 48-MHz USB clocks

CPU

x 3

SRC

x 1

3V66

x 5

PCI

REF

x 2

48M

x 2

x 10

Pin Configuration^[1]

Block Diagram

VDD_REF

REF0:1

REF_0

REF_1

VDD_REF

XIN

XOUT

VSS_REF

FS_B

VDD_A

VSS_A

VSS_IREF

IREF

XIN

XTAL

OSC

XOUT

PLL Ref Freq

VDD_CPU

CPUT[0:2], CPUC[0:2]

Divider

CPU_STP#

PCI_STP#

PLL1

Network

VDD_SRC

SRCT, SRCC

FS_A

PCIF0

PCIF1

PCIF2

CPU_STP#

PCI_STP#

VDD_CPU

CPUT2

CPUC2

VSS_CPU

CPUT1

CPUC1

VDD_CPU

CPUT0

CPUC0

VSS_SRC

SRCT

SRCC

VDD_SRC

VTT_PWRGD#

VDD_48

VSS_48

DOT_48

USB_48

SDATA

3V66_4/VCH

FS_[A:B]

VTT_PWRGD#

IREF

VDD_PCI

VSS_PCI

PCI0

VDD_3V66

3V66_[0:3]

PCI1

PCI2

PCI3

VDD_PCI

PCIF[0:2]

PLL2

PCI[0:6]

VDD_PCI

VSS_PCI

PCI4

3V66_4/VCH

PCI5

PCI6

PD#

VDD_48MHz

DOT_48

PD#

3V66_0

3V66_1

VDD_3V66

VSS_3V66

3V66_2

3V66_3

SCLK

USB_48

SDATA

SCLK

I C

Logic

56 SSOP/TSSOP

Note:

1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.

Cypress Semiconductor Corporation

Document #: 38-07445 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 2, 2006

12 3 4 5 6 7...17

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