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CY28346-2_05 PDF预览

CY28346-2_05

更新时间: 2024-01-21 01:33:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
20页 237K
描述
Clock Synthesizer with Differential CPU Outputs

CY28346-2_05 数据手册

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PRELIMINARY  
CY28346-2  
Clock Synthesizer with Differential CPU Outputs  
Features  
• Compliant with Intel® CK 408 Mobile Clock Synthesizer  
• Spread Spectrum electromagnetic interference (EMI)  
reduction  
specifications  
• 3.3V power supply  
• Dial-a-Frequencyfeatures  
• 3 differential CPU clocks  
• 10 copies of PCI clocks  
• 5/6 copies of 3V66 clocks  
• SMBus support with Read Back capabilities  
• Dial-a-dB™ features  
• Extended operating temperature range, 0°C to 85°C  
• 56-pin TSSOP packages  
Table 1. Frequency Table[1]  
CPU  
66BUFF(0:2)/  
3V66(0:4)  
66IN/  
USB/  
DOT  
48M  
48M  
48M  
48M  
48M  
48M  
48M  
S2  
1
1
1
1
0
0
0
0
S1  
0
0
1
1
0
0
1
1
S0  
0
1
0
1
0
1
0
1
(0:2)  
3V66  
66M  
66M  
66M  
66M  
66M  
66M  
66M  
66M  
3V66-5  
PCIF/PCI  
66IN/2  
66IN/2  
66IN/2  
66IN/2  
33 M  
33 M  
33 M  
33 M  
Hi-Z  
REF  
66M  
100M  
200M  
133M  
66M  
100M  
200M  
133M  
Hi-Z  
66IN  
66IN  
66IN  
66IN  
66M  
66M  
66M  
66M  
Hi-Z  
66-MHz clock input  
66-MHz clock input  
66-MHz clock input  
66-MHz clock input  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
Hi-Z  
66M  
66M  
66M  
66M  
Hi-Z  
48M  
Hi-Z  
TCLK/2  
M
M
0
0
0
1
Hi-Z  
TCLK/4  
TCLK/2  
TCLK/4  
TCLK/4  
TCLK/8  
TCLK  
Block Diagram  
Pin Configuration  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
REF  
VDD  
XIN  
XIN  
REF  
2
S1  
S0  
XOUT  
3
XOUT  
4
CPU_STP#  
CPUT0  
CPUC0  
VDD  
VSS  
CPUT(0:2)  
5
PLL1  
PCIF0  
CPUC(0:2)  
6
PCIF1  
7
PCIF2  
CPU_STP#  
8
CPUT1  
CPUC1  
VSS  
VDD  
IREF  
9
VSS  
VSSIREF  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
PCI0  
3V66_0  
S(0:2)  
VDD  
PCI1  
CPUT2  
CPUC2  
MULT0  
IREF  
PCI2  
3V66_1/VCH  
MULT0  
PCI3  
VDD  
VTT_PWRGD#  
PCI_STP#  
/2  
PCI(0:6)  
VSS  
VSSIREF  
S2  
PCI4  
PCI_F(0:2)  
48M_USB  
48M_DOT  
PCI5  
48M_USB  
48M_DOT  
VDD  
PLL2  
PCI6  
VDD  
VSS  
VSS  
66B0/3V66_2  
66B1/3V66_3  
66B2/3V66_4  
66IN/3V66_5  
PD#  
WD  
PD#  
3V66_1/VCH  
PCI_STP#  
3V66_0  
VDD  
Logic  
I2C  
SDATA  
SCLK  
Logic  
VSS  
66B[0:2]/3V66[2:4]  
66IN/3V66-5  
VDDA  
SCLK  
Power  
Up Logic  
VSSA  
VDDA  
SDATA  
VTT_PWRGD#  
Note:  
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a  
0 state will be latched into the devices internal state register.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07509 Rev. *B  
Revised March 11, 2005  

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