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CY28346-2 PDF预览

CY28346-2

更新时间: 2024-02-14 17:04:45
品牌 Logo 应用领域
SPECTRALINEAR 时钟
页数 文件大小 规格书
19页 169K
描述
Clock Synthesizer with Differential CPU Outputs

CY28346-2 数据手册

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CY28346-2  
Clock Synthesizer with Differential CPU Outputs  
Features  
• Compliant with Intel® CK 408 Mobile Clock Synthesizer  
specifications  
• Spread Spectrum electromagnetic interference (EMI)  
reduction  
• 3.3V power supply  
• Dial-a-Frequency£ features  
• 3 differential CPU clocks  
• 10 copies of PCI clocks  
• Dial-a-dB™ features  
• Extended operating temperature range, 0qC to 85qC  
• 56-pin TSSOP packages  
• 5/6 copies of 3V66 clocks  
• SMBus support with Read Back capabilities  
Table 1. Frequency Table[1]  
CPU  
(0:2)  
66BUFF(0:2)/  
3V66(0:4)  
66IN/  
3V66-5  
USB/  
DOT  
S2  
1
S1  
0
S0  
0
3V66  
66M  
PCIF/PCI  
66IN/2  
66IN/2  
66IN/2  
66IN/2  
33 M  
REF  
66M  
100M  
200M  
133M  
66M  
66IN  
66IN  
66IN  
66IN  
66M  
66-MHz clock input  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
Hi-Z  
48M  
48M  
1
0
1
66M  
66-MHz clock input  
1
1
0
66M  
66-MHz clock input  
48M  
1
1
1
66M  
66-MHz clock input  
48M  
0
0
0
66M  
66M  
66M  
48M  
0
0
1
100M  
200M  
133M  
Hi-Z  
66M  
66M  
33 M  
48M  
0
1
0
66M  
66M  
66M  
33 M  
48M  
0
1
1
66M  
66M  
66M  
33 M  
48M  
M
M
0
0
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
0
1
TCLK/2  
TCLK/4  
TCLK/4  
TCLK/4  
TCLK/8  
TCLK  
TCLK/2  
Block Diagram  
Pin Configuration  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
REF  
S1  
S0  
CPU_STP#  
CPUT0  
CPUC0  
VDD  
CPUT1  
CPUC1  
VSS  
VDD  
XIN  
XOUT  
XIN  
XOUT  
REF  
2
3
4
5
6
7
8
9
VSS  
PCIF0  
PCIF1  
PCIF2  
VDD  
VSS  
PCI0  
PCI1  
PCI2  
PCI3  
VDD  
VSS  
PCI4  
PCI5  
PCI6  
VDD  
VSS  
CPUT(0:2)  
CPUC(0:2)  
PLL1  
CPU_STP#  
IREF  
VSSIREF  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
3V66_0  
S(0:2)  
VDD  
CPUT2  
CPUC2  
MULT0  
IREF  
VSSIREF  
S2  
48M_USB  
48M_DOT  
VDD  
3V66_1/VCH  
MULT0  
VTT_PWRGD#  
PCI_STP#  
/2  
PCI(0:6)  
PCI_F(0:2)  
48M_USB  
48M_DOT  
PLL2  
VSS  
66B0/3V66_2  
66B1/3V66_3  
66B2/3V66_4  
66IN/3V66_5  
PD#  
VDDA  
VSSA  
VTT_PWRGD#  
WD  
Logic  
PD#  
3V66_1/VCH  
PCI_STP#  
3V66_0  
VDD  
VSS  
SCLK  
SDATA  
I2C  
Logic  
SDATA  
SCLK  
66B[0:2]/3V66[2:4]  
66IN/3V66-5  
Power  
Up Logic  
VDDA  
Note:  
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a  
0 state will be latched into the devices internal state register.  
Rev 1.0, November 20, 2006  
Page 1 of 19  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  

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