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CY28344 PDF预览

CY28344

更新时间: 2024-11-18 04:38:03
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
21页 217K
描述
FTG for Intel Pentium 4 CPU and Chipsets

CY28344 数据手册

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CY28344  
FTG for Intel Pentium 4 CPU and Chipsets  
• Capable of generating system RESET after a Watchdog  
timer time-out occurs or a change in output frequency  
via SMBus interface  
Features  
• Compatible to Intel® CK-Titan and CK-408 Clock  
Synthesizer/Driver Specifications  
• Support SMBus byte Read/Write and block Read/Write  
operations to simplify system BIOS development  
• Vendor ID and Revision ID support  
• Programmable drive strength support  
• Programmable output skew support  
• Power management control inputs  
Available in 48-pin SSOP  
• System frequency synthesizer for Intel Brookdale (845)  
and Brookdale G Pentium® 4 Chipsets  
• Programmable clock output frequency with less than  
1MHz increment  
• Integrated fail-safe Watchdog timer for system  
recovery  
• Automatically switch to HW-selected or  
SW-programmed clock frequency when Watchdog  
timer time-out  
CPU  
×3  
3V66  
×4  
PCI  
×9  
REF  
×1  
48M  
×2  
Pin Configuration[1]  
Block Diagram  
VDD_REF  
XTAL  
REF_2X  
VDD_REF  
X1  
X2  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
REF_2X/FS2^  
CPU0  
CPU0#  
VDD_CPU  
CPU1  
CPU1#  
GND_CPU  
VDD_CPU  
CPU2  
CPU2#  
MULTSEL0  
IREF  
GND_CPU  
48MHz/FS3^  
24_48MHz  
VDD_48MHz  
GND_48MHz  
3V66_0/VCH_CLK/FS4^  
VDD_3V66  
GND_3V66  
SCLK  
SDATA  
VTTPWRGD/PD#*  
GND_CORE  
X1  
OSC  
X2  
PLL Ref Freq  
Divider  
GND_REF  
^FS0/PCI_F0  
^FS1/PCI_F1  
VDD_PCI  
GND_PCI  
PCI0  
VDD_CPU  
PLL 1  
Network  
CPU0:2, CPU0:2#,  
FS0:4  
MULTSEL0  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
PCI1  
PCI2  
PCI3  
VDD_3V66  
3V66_1:3  
VDD_PCI  
GND_PCI  
PCI4  
VDD_3V66  
3V66_0/VCH_CLK  
VTTPWRGD/PD#  
PCI5  
PCI6  
VDD_PCI  
PCI_F0:1  
VDD_3V66  
GND_3V66  
3V66_1  
3V66_2  
3V66_3  
RST#  
PCI0:6  
VDD_48MHz  
48MHz  
PLL2  
VDD_CORE  
24_48MHz  
RST#  
SSOP-48  
2
SDATA  
SCLK  
SMBus  
Logic  
Note:  
1. Signals marked with “*” and “^,” respectively, have internal pull-up and  
pull-down resistors.  
Rev 1.0, November 21, 2006  
2200 Laurelwood Road, Santa Clara, CA 95054  
Page 1 of 21  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  

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