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CY28342 PDF预览

CY28342

更新时间: 2024-11-18 04:38:03
品牌 Logo 应用领域
SPECTRALINEAR 时钟
页数 文件大小 规格书
21页 259K
描述
High-performance SiS645/650 Pentium㈢ 4-Clock Synthesizer

CY28342 数据手册

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CY28342  
High-performance SiS645/650 Pentium® 4-Clock Synthesizer  
Features  
• Supports Pentium£ 4-type CPUs  
• SMBus support with read-back capabilities  
• Spread Spectrum EMI reduction  
• Dial-a-Frequency® features  
• Dial-a-Ratio™ features  
• 3.3V power supply  
• Eight copies of PCI clocks  
• One 48 MHz USB clock  
• Two copies of ZCLK clocks  
• One 48 MHz/24MHz programmable SIO clock  
• Two differential CPU clock pairs  
• Dial-a-dB® features  
• 48-pin SSOP and TSSOP packages  
• Watchdog Function  
Pin Configuration[1]  
Block Diagram  
XIN  
XOUT  
REF(0:2)  
VDDSD  
SDCLK  
VSSSD  
VDDR  
**FS0/REF0  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
2
**FS1/REF1  
**FS2/REF2  
VSSR  
3
CPU(0:1)T  
CPU(0:1)C  
4
PLL1  
CPU_STP#*  
CPU1T  
CPU1C  
VDDC  
VSSC  
5
XIN  
XOUT  
6
CPU_STP#  
IREF  
SDCLK  
7
VSSZ  
ZCLK0  
ZCLK1  
8
9
CPU0T  
CPU0C  
IREF  
VSSA  
VDDA  
AGP(0:1)  
Power  
on  
Latch  
FS(0:4)  
10  
11  
12  
13  
14  
15  
VDDZ  
*SRESET#/PCI_STP#  
ZCLK(0:1)  
MULT0  
VDDP  
VTTPWRGD  
SCLK  
SDATA  
PD#/VTTPWRGD*  
VSSAGP  
AGP0  
/2  
**FS3/PCI_F0  
**FS4/PCI_F1  
PCI(0:5)  
PCI_STP#  
PCI0 16  
PCI1  
17  
PCI_F(0:1)  
48M  
PLL2  
VSSP  
VDDP  
PCI2  
PCI3  
PCI4  
18  
19  
20  
21  
22  
23  
24  
AGP1  
48M_24M#  
VDDAGP  
VDD48M  
48M  
WD  
Logic  
PD#  
SRESET#  
24_48M/MULT0*  
PCI5  
I2C  
Logic  
SDATA  
SCLK  
VSS48M  
VSSP  
48 Pin SSOP andf TSSOP  
Note:  
1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.  
Rev 1.0, November 20, 2006  
Page 1 of 21  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  

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