5秒后页面跳转
CY28341ZC PDF预览

CY28341ZC

更新时间: 2024-11-20 22:15:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管双倍数据速率
页数 文件大小 规格书
21页 191K
描述
Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems

CY28341ZC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:6 X 14 MM, TSSOP2-56
针数:56Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.77Is Samacsys:N
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:14 mm端子数量:56
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5,2.5/3.3,3.3 V
主时钟/晶体标称频率:14.31818 MHz认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Clock Generators
最大压摆率:195 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.1 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

CY28341ZC 数据手册

 浏览型号CY28341ZC的Datasheet PDF文件第2页浏览型号CY28341ZC的Datasheet PDF文件第3页浏览型号CY28341ZC的Datasheet PDF文件第4页浏览型号CY28341ZC的Datasheet PDF文件第5页浏览型号CY28341ZC的Datasheet PDF文件第6页浏览型号CY28341ZC的Datasheet PDF文件第7页 
CY28341  
Universal Single-Chip Clock Solution for VIA P4M266/KM266  
DDR Systems  
Features  
Table 1. Frequency Selection Table  
FS(3:0)  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1100  
1111  
CPU  
66.80  
AGP  
66.80  
66.80  
60.00  
66.67  
72.00  
70.00  
64.00  
70.00  
77.00  
73.33  
60.00  
60.00  
60.00  
66.67  
66.67  
66.67  
PCI  
• Supports VIA P4M266/KM266 chipsets  
• Supports Pentium® 4, Athlon™ processors  
• Supports two DDR DIMMS  
• Supports three SDRAMS DIMMS at 100 MHz  
• Provides:  
33.40  
33.40  
30.00  
33.33  
36.00  
35.00  
32.00  
35.00  
38.50  
36.67  
30.00  
30.00  
30.00  
33.33  
33.33  
33.33  
100.00  
120.00  
133.33  
72.00  
105.00  
160.00  
140.00  
77.00  
110.00  
180.00  
150.00  
90.00  
100.00  
200.00  
133.33  
— Two different programmable CPU clock pairs  
— Six differential SDRAM DDR pairs  
— Three low-skew/low-jitter AGP clocks  
— Seven low-skew/low-jitter PCI clocks  
— One 48M output for USB  
— One programmable 24M or 48M for SIO  
• Dial-a-Frequency™ and Dial-a-dB features  
• SpreadSpectrumforbestelectromagneticinterference  
(EMI) reduction  
• Watchdog feature for systems recovery  
• SMBus-compatible for programmability  
• 56-pin SSOP and TSSOP packages  
[1]  
Block Diagram  
Pin Configuration  
VDDR  
XIN  
XOUT  
1
2
3
4
5
6
7
8
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
*FS0/REF0  
VSSR  
VTTPWRGD#/REF1  
VDDR  
VSSC  
CPUT/CPUOD_T  
CPUC/CPUOD_C  
VDDC  
REF(0:1)  
VDDI  
XTAL  
FS2  
REF0  
XIN  
XOUT  
VDDAGP  
AGP0  
*SELP4_K7/AGP1  
AGP2  
VSSAGP  
**FS1/PCI_F  
**SELSDR_DDR/PCI1  
CPUCS_T/C  
FS0  
VDDC  
SELP4_K7#  
VDDI  
CPU(0:1)/CPU0D_T/C  
PLL1  
CPUCS_C  
CPUCS_T  
VSSI  
FBOUT  
BUF_IN  
DDRT0/SDRAM0  
DDRC0/SDRAM1  
DDRT1/SDRAM2  
DDRC1/SDRAM3  
VDDD  
9
VDDPCI  
PCI(3:6)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
FS3 FS1  
*MULTSEL/PCI2  
VSSPCI  
PCI3  
PCI_F  
MULTSEL  
PD#  
PCI2  
PCI4  
VDDPCI  
PCI5  
PCI1  
VDDAGP  
AGP(0:2)  
PCI6  
VSSD  
VSS48M  
**FS3/48M  
**FS2/24_48M  
VDD48M  
VDD  
VSS  
IREF  
*PD#/SRESET#  
SCLK  
DDRT2/SDRAM4  
DDRC2/SDRAM5  
DDRT3/SDRAM6  
DDRC3/SDRAM7  
VDDD  
VDD48M  
48M  
SDATA  
SCLK  
SMBus  
PLL2  
/ 2  
WDEN  
VSSD  
24_48M  
DDRT4/SDRAM8  
DDRC4/SDRAM9  
DDRT5/SDRAM10  
DDRC5/SDRAM11  
SRESET#  
VDDD  
WD  
SDATA  
SELSDR_DDR  
FBOUT  
S2D  
DDRT(0:5)/SDRAM(0,2,4,6,8,10)  
DDRC(0:5)/SDRAM(1,3,5,7,9,11)  
56 pin SSOP  
Buf_IN  
CONVERT  
Note:  
1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07367 Rev. *A  
Revised December 26, 2002  

与CY28341ZC相关器件

型号 品牌 获取价格 描述 数据表
CY28341ZC-2 CYPRESS

获取价格

Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR
CY28341ZC-2 SILICON

获取价格

Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, 6 X 12 MM, MO-153, TSSOP2-56
CY28341ZC-2 SPECTRALINEAR

获取价格

Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR
CY28341ZC-2T SPECTRALINEAR

获取价格

Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR
CY28341ZC-2T CYPRESS

获取价格

Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR
CY28341ZC-3 SPECTRALINEAR

获取价格

Universal Clock Chip for VIA⑩P4M/KT/KM400A DD
CY28341ZC-3 CYPRESS

获取价格

Universal Clock Chip for VIA⑩P4M/KT/KM400A DD
CY28341ZC-3T SPECTRALINEAR

获取价格

Universal Clock Chip for VIA⑩P4M/KT/KM400A DD
CY28341ZC-3T CYPRESS

获取价格

Universal Clock Chip for VIA⑩P4M/KT/KM400A DD
CY28341ZCT CYPRESS

获取价格

Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems