Datasheet > CY28339ZXC

CY28339ZXC

更新时间： 2024-09-23 03:15:55

品牌	Logo	应用领域
SPECTRALINEAR		晶体外围集成电路光电二极管手机时钟
页数	文件大小	规格书
17页	160K
描述
Intel CK408 Mobile Clock Synthesizer

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CY28339ZXC 数据手册

CY28339

Intel^£CK408 Mobile Clock Synthesizer

Features

• Compliant with Intel^®CK 408 rev 1.1 Mobile Clock

Synthesizer specifications

• One VCH clock

• One reference clock at 14.318 MHz

• SMBus support with read-back capabilities

• 3.3V power supply

• Two differential CPU clocks

• Ideal Lexmark profile Spread Spectrum electromag-

netic interference (EMI) reduction

• Nine copies of PCI clocks

• Three copies configurable PCI free-running clocks

• Two 48 MHz clocks (USB, DOT)

• Five/six copies of 3V66 clocks

• Dial-a-Frequency™ features

• Dial-a-dB™ features

• 48-pin TSSOP package

Table 1. Frequency Table^[1]

66BUFF(0:2)/

3V66(0:4)

66IN

S1 CPU (1:2)

3V66

66M

66IN/3V66–5

66-MHz clock input

66-MHZ clock input

66M

PCIF, PCI

66IN/2

33 M

REF

USB/ DOT

48M

100M

133M

14.318M

TCLK

66M

66IN

48M

100M

66M

48M

133M

66M

33 M

48M

TCLK/2

TCLK/4

TCLK/8

TCLK/2

Block Diagram

Pin Configuration

VDD_REF

XTAL

OSC

PWR

REF

Top View

PLL Ref Freq

VDD_REF

XIN

XOUT

REF

Divider

PLL 1

GND_REF

PCI7

Network

CPU_STOP#

VDD_CPU

CPUT1:2

Stop

Clock

Control

PWR

Gate

PCI8

PCIF

VDD_CPU

CPUT1

S1:2

VTT_PWRGD##

CPU_STOP#

CPUC1:2

GND_PCI

PCI0

CPUC1

VDD_PCI

PCIF

GND_CPU

PWR

PCI1

VDD_CPU

CPUT2

PCI0:2

PCI4:8

Stop

Clock

Control

PCI2

VDD_PCI

PCI4

CPUC2

IREF

PCI_STOP#

PD#

PCI5

PCI6

VDD_3V66

3V66_0:1

USB_48MHz

PWR

VDD_3V66

GND_3V66

DOT_48MHz

3V66_2:4/

66BUFF0:2

VDD_48 MHz

GND_48 MHz

PWR

3V66_5/ 66IN

66BUFF0/3V66_2

66BUFF1/3V66_3

66BUFF2/3V66_4

3V66_1/VCH

PCI_STOP#

3V66_0

66IN/3V66_5

VDD_48MHz

USB (48MHz)

PLL 2

PWR

PD#

VDD_3V66

VDD_CORE

DOT (48MHz)

GND_3V66

SCLK

GND_CORE

VCH_CLK/ 3V66_1

VTT_PWRGD#

SDATA

SCLK

SMBus

Logic

Note:

1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a

0 state will be latched into the device’s internal state register.

Rev 1.0, November 25, 2006

Page 1 of 17

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

12 3 4 5 6 7...17

中文翻译

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与CY28339ZXC相关器件

型号	品牌	获取价格	描述	数据表
CY28339ZXCT	SILICON	获取价格	Processor Specific Clock Generator, 133MHz, CMOS, PDSO48, 0.240 INCH, LEAD FREE, TSSOP2-48
CY28341	SPECTRALINEAR	获取价格	Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems
CY28341	CYPRESS	获取价格	Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems
CY28341-2	SPECTRALINEAR	获取价格	Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR
CY28341-2	CYPRESS	获取价格	Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems
CY28341-2_05	CYPRESS	获取价格	Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR
CY28341-3	SPECTRALINEAR	获取价格	Universal Clock Chip for VIA⑩P4M/KT/KM400A DD
CY28341-3	CYPRESS	获取价格	Universal Clock Chip for VIA⑩P4M/KT/KM400A DD
CY28341OC	SPECTRALINEAR	获取价格	Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems
CY28341OC	CYPRESS	获取价格	Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems

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