Datasheet > CY28326OCT

CY28326OCT

更新时间： 2024-11-17 02:56:07

品牌	Logo	应用领域
SPECTRALINEAR		晶体外围集成电路光电二极管时钟
页数	文件大小	规格书
22页	224K
描述
FTG for VIA PT880 Serial Chipset

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中文翻译

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数据手册

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CY28326OCT 数据手册

CY28326

FTG for VIA PT880 Serial Chipset

Features

• Supports P4^£CPUs

• Three differential CPU clock pairs

• 3.3V power supply

• SMBus support with Byte Write/Block Read/Write

capabilities

• Ten copies of PCI clocks

• Spread Spectrum EMI reduction

• Dial-A-Frequency^®features

• Auto Ratio features

• One 48 MHz USB clock

• Two copies of 25 MHz for SRC/LAN clocks

• One 48 MHz/24 MHz programmable SIO clock

• 48-pin SSOP package

Pin Configuration^[1]

Block Diagram

XIN

REF[0:2]

**FSA/REF0

**FSB/REF1

VDDREF

VDDA

VSSA

IREF

XOUT

XIN

XOUT

CPUT2

CPUC2

VSSCPU

CPUT1

CPUC1

CPUT[0:2]

CPUC[0:2]

PLL1

VSSREF

*FSC/PCIF0

CPU_STP#

IREF

25MHz[0:1]

AGP[0:2]

*FSD/PCIF1

*Mode/PCIF2

VDDCPU

CPUT0

VDDPCI

VSSPCI

PCI0

Power

CPUC0

VSSSRC

25MHz1

FS[A:D]

Latch

PCI1

25MHz0

PCI2

PCI3

VTTPWRGD#

PCI_STP#

VDDSRC

PCI[0:6]

*VTT_PWRGD/*PD#

PCI4

VDDPCI

SDATA

PCI_F[0:2]

48MHz

VSSPCI

*(PCI_STP#)/Ratio0/PCI5

*(CPU_STP#)/Ratio1/PCI6

48MHz

SCLK

SRESET#

PLL2

AGP2

MODE

PD#

24_48MHz

VSSAGP

VDDAGP

AGP1/*RatioSel

**24_48_SEL/24_48MHz

VSS48

SRESET

Logic

AGP0

VDD48

I2C

SDATA

SCLK

48 Pin SSOP

Logic

Note:

1. Pins marked with [*] have internal 150k:ꢀpull-up resistors. Pins marked with [**] have internal 150k:ꢀpull-down resistors.

Rev 1.0, November 20, 2006

Page 1 of 22

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

12 3 4 5 6 7...22

中文翻译

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