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CY28326OCT PDF预览

CY28326OCT

更新时间: 2024-02-01 19:00:54
品牌 Logo 应用领域
SPECTRALINEAR 晶体外围集成电路光电二极管时钟
页数 文件大小 规格书
22页 224K
描述
FTG for VIA PT880 Serial Chipset

CY28326OCT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.52
JESD-30 代码:R-PDSO-G48长度:15.875 mm
湿度敏感等级:1端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:333.3 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
主时钟/晶体标称频率:14.31818 MHz认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

CY28326OCT 数据手册

 浏览型号CY28326OCT的Datasheet PDF文件第2页浏览型号CY28326OCT的Datasheet PDF文件第3页浏览型号CY28326OCT的Datasheet PDF文件第4页浏览型号CY28326OCT的Datasheet PDF文件第5页浏览型号CY28326OCT的Datasheet PDF文件第6页浏览型号CY28326OCT的Datasheet PDF文件第7页 
CY28326  
FTG for VIA PT880 Serial Chipset  
Features  
• Supports P4£ CPUs  
• Three differential CPU clock pairs  
• 3.3V power supply  
• SMBus support with Byte Write/Block Read/Write  
capabilities  
• Ten copies of PCI clocks  
• Spread Spectrum EMI reduction  
• Dial-A-Frequency® features  
• Auto Ratio features  
• One 48 MHz USB clock  
• Two copies of 25 MHz for SRC/LAN clocks  
• One 48 MHz/24 MHz programmable SIO clock  
• 48-pin SSOP package  
Pin Configuration[1]  
Block Diagram  
XIN  
REF[0:2]  
**FSA/REF0  
**FSB/REF1  
VDDREF  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDA  
VSSA  
IREF  
XOUT  
2
3
4
XIN  
XOUT  
CPUT2  
CPUC2  
VSSCPU  
CPUT1  
CPUC1  
CPUT[0:2]  
CPUC[0:2]  
PLL1  
5
VSSREF  
*FSC/PCIF0  
6
CPU_STP#  
IREF  
7
25MHz[0:1]  
AGP[0:2]  
*FSD/PCIF1  
8
*Mode/PCIF2  
9
VDDCPU  
CPUT0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VDDPCI  
VSSPCI  
PCI0  
Power  
CPUC0  
VSSSRC  
25MHz1  
on  
FS[A:D]  
Latch  
PCI1  
25MHz0  
PCI2  
PCI3  
VTTPWRGD#  
PCI_STP#  
VDDSRC  
/2  
PCI[0:6]  
*VTT_PWRGD/*PD#  
PCI4  
VDDPCI  
SDATA  
PCI_F[0:2]  
48MHz  
VSSPCI  
*(PCI_STP#)/Ratio0/PCI5  
*(CPU_STP#)/Ratio1/PCI6  
48MHz  
SCLK  
SRESET#  
PLL2  
AGP2  
MODE  
PD#  
24_48MHz  
VSSAGP  
VDDAGP  
AGP1/*RatioSel  
**24_48_SEL/24_48MHz  
VSS48  
WD  
SRESET  
Logic  
AGP0  
VDD48  
I2C  
SDATA  
SCLK  
48 Pin SSOP  
Logic  
Note:  
1. Pins marked with [*] have internal 150k:ꢀpull-up resistors. Pins marked with [**] have internal 150k:ꢀpull-down resistors.  
Rev 1.0, November 20, 2006  
Page 1 of 22  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  

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