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CY28326OC

更新时间: 2024-11-18 21:54:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
23页 289K
描述
FTG for VIA PT880 Serial Chipset

CY28326OC 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.52Is Samacsys:N
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:15.875 mm湿度敏感等级:1
端子数量:48最高工作温度:70 °C
最低工作温度:最大输出时钟频率:333.3 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
电源:3.3 V主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Clock Generators最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5057 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

CY28326OC 数据手册

 浏览型号CY28326OC的Datasheet PDF文件第2页浏览型号CY28326OC的Datasheet PDF文件第3页浏览型号CY28326OC的Datasheet PDF文件第4页浏览型号CY28326OC的Datasheet PDF文件第5页浏览型号CY28326OC的Datasheet PDF文件第6页浏览型号CY28326OC的Datasheet PDF文件第7页 
CY28326  
FTG for VIA PT880 Serial Chipset  
Features  
• Supports P4CPUs  
• Three differential CPU clock pairs  
• 3.3V power supply  
• SMBus support with Byte Write/Block Read/Write  
capabilities  
• Ten copies of PCI clocks  
• One 48 MHz USB clock  
• Two copies of 25 MHz for SRC/LAN clocks  
• One 48 MHz/24 MHz programmable SIO clock  
• Spread Spectrum EMI reduction  
• Dial-A-Frequency® features  
• Auto Ratio features  
• 48-pin SSOP package  
Pin Configuration[1]  
Block Diagram  
XIN  
REF[0:2]  
**FSA/REF0  
**FSB/REF1  
VDDREF  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDA  
VSSA  
IREF  
CPUT2  
CPUC2  
VSSCPU  
CPUT1  
CPUC1  
XOUT  
XIN  
XOUT  
CPUT[0:2]  
CPUC[0:2]  
PLL1  
VSSREF  
*FSC/PCIF0  
CPU_STP#  
IREF  
25MHz[0:1]  
AGP[0:2]  
*FSD/PCIF1  
*Mode/PCIF2  
9
VDDCPU  
CPUT0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VDDPCI  
VSSPCI  
PCI0  
Power  
CPUC0  
VSSSRC  
on  
FS[A:D]  
25MHz1  
Latch  
PCI1  
25MHz0  
VDDSRC  
*VTT_PWRGD/*PD#  
PCI2  
VTTPWRGD#  
PCI_STP#  
PCI3  
/2  
PCI[0:6]  
PCI4  
VDDPCI  
SDATA  
PCI_F[0:2]  
48MHz  
VSSPCI  
*(PCI_STP#)/Ratio0/PCI5  
*(CPU_STP#)/Ratio1/PCI6  
48MHz  
**24_48_SEL/24_48MHz  
VSS48  
SCLK  
PLL2  
SRESET#  
AGP2  
MODE  
PD#  
24_48MHz  
VSSAGP  
VDDAGP  
AGP1/*RatioSel  
WD  
Logic  
SRESET  
AGP0  
VDD48  
I2C  
Logic  
SDATA  
SCLK  
48 Pin SSOP  
Note:  
1. Pins marked with [*] have internal 150kpull-up resistors. Pins marked with [**] have internal 150kpull-down resistors.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07616 Rev. *A  
Revised June 22, 2004  

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