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CY28325OXC-3T PDF预览

CY28325OXC-3T

更新时间: 2024-09-20 22:10:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 266K
描述
FTG for VIA Pentium 4 Chipsets

CY28325OXC-3T 数据手册

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CY28325-3  
FTG for VIA™ Pentium 4™ Chipsets  
• Vendor ID and Revision ID support  
• Programmable-drive strength support  
• Programmable-output skew support  
• Three copies AGP Clocks  
• Power management control inputs  
• Available in 48-pin SSOP  
Features  
• Spread Spectrum Frequency Timing Generator for VIA  
PT/M 266-800 Pentium4 Chipsets  
• Programmableclockoutputfrequencywithlessthan1 MHz  
increment  
• Integrated fail-safe Watchdog Timer for system recovery  
• Selectable hardware or software-programmed clock  
frequency when Watchdog Timer time-out  
CPU  
x 3  
AGP  
x 3  
PCI  
x 9  
REF  
x 1  
APIC  
x 2  
48M  
x 1  
24_48M  
x 1  
• Capable to generate system RESET after a Watchdog  
Timer time-out occurs or a change in output frequency via  
SMBus interface  
• Support SMBus Byte Read/Write and Block Read/Write  
operations to simplify system BIOS development  
[1]  
Block Diagram  
Pin Configuration  
VDD_REF  
SSOP-48  
X1  
X2  
XTAL  
OSC  
REF  
PLL Ref Freq  
VDD_CPU_CS (2.5V)  
*FS4/REF  
VDD_REF  
GND_REF  
X1  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDD_APIC  
GND_APIC  
APIC0  
Divider  
CPUT_CS, CPUC_CS  
PLL 1  
Stop  
Network  
VDD_CPU (3.3V)  
2
Clock  
Control  
CPUT_0,1, CPUC_0,1  
3
4
APIC1  
*(FS0:4)  
VTT_PWRGD#  
X2  
5
GND_CPU  
*CPU_STOP#  
VDD_48MHz  
6
VDD_CPU_CS(2.5V)  
CPUT_CS_F  
CPUC_CS_F  
CPUT_0  
*MULTSEL1  
7
*FS3/48MHz  
VDD_APIC  
APIC0:1  
8
*FS2/24_48MHz  
GND_48MHz  
*FS0/PCI_F  
*FS1/PCI1  
*MULT_SEL1/PCI2  
GND_PCI  
PCI3  
9
VDD_AGP  
AGP0:2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CPUC_0  
VDD_CPU(3.3V)  
IREF  
GND_CPU  
CPUT_1  
VDD_PCI  
PCI_F  
PCI4  
CPUC_1  
PD#  
Stop  
Clock  
PCI1:8  
VDD_PCI  
PCI5  
VTT_PWRGD#  
CPU_STOP#*  
PCI_STOP#*  
RST#  
Control  
*PCI_STOP#  
PCI6  
PCI7  
GND_PCI  
PCI8  
SDATA  
SCLK  
*PD#  
AGP2  
AGP0  
AGP1  
VDD_48MHz  
48MHz  
VDD_AGP  
GND_AGP  
PLL2  
24_48MHz  
RST#  
2
SDATA  
SCLK  
SMBus  
Logic  
Note:  
1. Pins marked with [*] have internal pull-up resistors. Pins marked with[^] have internal pull-down resistors.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07590 Rev. *.*  
Revised May 12, 2004  

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