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CY28325OXC-3T PDF预览

CY28325OXC-3T

更新时间: 2024-11-17 02:56:03
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
18页 206K
描述
FTG for VIA⑩ Pentium 4⑩ Chipsets

CY28325OXC-3T 数据手册

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CY28325-3  
FTG for VIA™ Pentium 4™ Chipsets  
• Support SMBus Byte Read/Write and Block Read/Write  
operations to simplify system BIOS development  
Features  
Spread Spectrum Frequency Timing Generator for VIA  
PT/M 266-800 Pentium£ 4 Chipsets  
• Vendor ID and Revision ID support  
• Programmable-drive strength support  
• Programmable-output skew support  
• Three copies AGP Clocks  
• Programmable clock output frequency with less than  
1 MHz increment  
• Integrated fail-safe Watchdog Timer for system  
recovery  
• Power management control inputs  
• Available in 48-pin SSOP  
• Selectable hardware or software-programmed clock  
frequency when Watchdog Timer time-out  
• Capable to generate system RESET after a Watchdog  
Timer time-out occurs or a change in output frequency  
via SMBus interface  
CPU  
x 3  
AGP  
x 3  
PCI  
x 9  
REF  
x 1  
APIC  
x 2  
48M  
x 1  
24_48M  
x 1  
[1]  
Block Diagram  
Pin Configuration  
VDD_REF  
SSOP-48  
X1  
XTAL  
OSC  
REF  
X2  
PLL Ref Freq  
VDD_CPU_CS (2.5V)  
*FS4/REF  
VDD_REF  
GND_REF  
X1  
X2  
VDD_48MHz  
*FS3/48MHz  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDD_APIC  
GND_APIC  
APIC0  
APIC1  
GND_CPU  
VDD_CPU_CS(2.5V)  
CPUT_CS_F  
CPUC_CS_F  
CPUT_0  
CPUC_0  
VDD_CPU(3.3V)  
IREF  
GND_CPU  
CPUT_1  
CPUC_1  
VTT_PWRGD#  
CPU_STOP#*  
PCI_STOP#*  
RST#  
SDATA  
SCLK  
AGP2  
AGP1  
GND_AGP  
Divider  
CPUT_CS, CPUC_CS  
VDD_CPU (3.3V)  
CPUT_0,1, CPUC_0,1  
PLL 1  
Stop  
Clock  
Control  
Network  
*(FS0:4)  
VTT_PWRGD#  
*CPU_STOP#  
*MULTSEL1  
VDD_APIC  
APIC0:1  
*FS2/24_48MHz  
GND_48MHz  
*FS0/PCI_F  
*FS1/PCI1  
*MULT_SEL1/PCI2  
GND_PCI  
PCI3  
9
VDD_AGP  
AGP0:2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VDD_PCI  
PCI_F  
PCI4  
PD#  
Stop  
Clock  
Control  
PCI1:8  
VDD_PCI  
PCI5  
PCI6  
*PCI_STOP#  
PCI7  
GND_PCI  
PCI8  
*PD#  
AGP0  
VDD_AGP  
VDD_48MHz  
48MHz  
PLL2  
24_48MHz  
RST#  
2
SDATA  
SCLK  
SMBus  
Logic  
Note:  
1. Pins marked with [*] have internal pull-up resistors. Pins marked with[^] have internal pull-down resistors.  
Rev 1.0, November 21, 2006  
Page 1 of 18  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  

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