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CY25402_11 PDF预览

CY25402_11

更新时间: 2024-09-30 09:41:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
14页 208K
描述
Two PLL Programmable Clock Generator with Spread Spectrum

CY25402_11 数据手册

 浏览型号CY25402_11的Datasheet PDF文件第2页浏览型号CY25402_11的Datasheet PDF文件第3页浏览型号CY25402_11的Datasheet PDF文件第4页浏览型号CY25402_11的Datasheet PDF文件第5页浏览型号CY25402_11的Datasheet PDF文件第6页浏览型号CY25402_11的Datasheet PDF文件第7页 
CY25402/CY25422/CY25482  
Two PLL Programmable Clock Generator  
with Spread Spectrum  
AbilitytosynthesizenonstandardfrequencieswithFractional-N  
capability  
Features  
Two fully integrated phase locked loops (PLLs)  
Three clock outputs with programmable drive strength  
Glitch-free outputs while frequency switching  
8-pin small outline integrated circuit (SOIC) package  
Commercial and Industrial temperature ranges  
Input frequency range  
External crystal: 8 to 48 MHz  
External reference: 8 to 166 MHz clock  
Reference clock input voltage range  
2.5 V, 3.0 V, and 3.3 V for CY25482  
1.8 V for CY25402 and CY25422  
Benefits  
Wide operating output frequency range  
3 to 166 MHz  
Multiple high performance PLLs allow synthesis of unrelated  
frequencies  
Nonvolatile programming for personalization of PLL  
frequencies, spread spectrum characteristics, drive strength,  
crystal load capacitance, and output frequencies  
Programmable spread spectrum with center and down spread  
option and lexmark and linear modulation profiles  
VDD supply voltage options:  
2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482  
1.8 V for CY25422  
Application specific programmableEMIreduction usingspread  
spectrum for clocks  
Programmable PLLs for system frequency margin tests  
Selectable output clock voltages independent of VDD  
2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482  
1.8 V for CY25422  
:
Meets critical timing requirements in complex system designs  
Suitability for PC, consumer, portable, and networking  
applications  
Frequency select feature with option to select four different  
frequencies  
Capable of zero parts per million (PPM) frequency synthesis  
Power-down, Output Enable, and SS ON/OFF controls  
Low jitter, high accuracy outputs  
error  
Uninterrupted system operation during clock frequency switch  
Application compatibility in standard and low power systems  
Block Diagram  
Crossbar  
XIN/  
CLK1  
Output  
Switch  
EXCLKIN  
PLL 1  
(SS)  
OSC  
Dividers  
and  
XOUT  
MUX  
and  
REFOUT  
CLK2  
Drive  
PLL 2  
(SS)  
Control  
Logic  
Strength  
Control  
FS0  
FS1  
SSON  
PD#/OE  
Cypress Semiconductor Corporation  
Document #: 001-12565 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 20, 2011  

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