Datasheet > CY25402_07

CY25402_07

更新时间： 2024-09-30 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
10页	259K
描述
Two PLL Programmable Clock Generator with Spread Spectrum

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中文翻译

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数据手册

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CY25402_07 数据手册

CY25402/CY25422/CY25482

Two PLL Programmable Clock Generator

with Spread Spectrum

■ Three clock outputs with Programmable drive strength

■ Glitch-free outputs while frequency switching

■ 8-pin SOIC package

Features

■ Two fully integrated phase locked loops (PLLs)

■ Input frequency range

■ Commercial and Industrial temperature ranges

❐ External crystal: 8 to 48 MHz

❐ External reference: 8 to 166 MHz clock

Benefits

■ Reference Clock input voltage range

❐ 2.5V, 3.0V, and 3.3V for CY25482

❐ 1.8V for CY25402 and CY25422

■ Multiple high performance PLLs allow synthesis of unrelated

frequencies

■ Wide operating output frequency range

❐ 3 to 166 MHz

■ Nonvolatile programming for personalization of PLL

frequencies,spreadspectrumcharacteristics,drivestrength,

crystal load capacitance, and output frequencies

■ Programmable Spread Spectrum with Center and Down

Spread option and Lexmark and Linear modulation profiles

■ Application specific Programmable EMI reduction using

Spread Spectrum for clocks

■ VDD supply voltage options:

❐ 2.5V, 3.0V, and 3.3V for CY25402 and CY25482

❐ 1.8V for CY25422

■ Programmable PLLs for system frequency margin tests

■ Meets critical timing requirements in complex system

designs

■ Selectable output clock voltages independent of VDD:

❐ 2.5V, 3.0V, and 3.3V for CY25402 and CY25482

❐ 1.8V for CY25422

■ Suitability for PC, consumer, portable, and networking appli-

cations

■ Frequency Select feature with option to select four different

frequencies

■ Capable of Zero PPM frequency synthesis error

■ Uninterrupted system operation during clock frequency

■ Power Down, Output Enable, and SS ON/OFF controls

■ Low jitter, high accuracy outputs

switch

■ Application compatibility in standard and low power systems

■ Ability to synthesize nonstandard frequencies with

Fractional-N capability

Block Diagram

Crossbar

XIN/

CLK1

Output

Switch

EXCLKIN

PLL 1

(SS)

OSC

Dividers

and

XOUT

MUX

and

REFOUT

CLK2

Drive

PLL 2

(SS)

Control

Logic

Strength

Control

FS0

FS1

SSON

PD#/OE

Cypress Semiconductor Corporation

Document #: 001-12565 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 13, 2007

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与CY25402_07相关器件

型号	品牌	获取价格	描述	数据表
CY25402_11	CYPRESS	获取价格	Two PLL Programmable Clock Generator with Spread Spectrum
CY25402FSXC	CYPRESS	获取价格	Two PLL Programmable Clock Generator with Spread Spectrum
CY25402FSXI	CYPRESS	获取价格	Two PLL Programmable Clock Generator with Spread Spectrum
CY25402FSXIT	CYPRESS	获取价格	Two PLL Programmable Clock Generator with Spread Spectrum
CY25402SXC	CYPRESS	获取价格	Two PLL Programmable Clock Generator with Spread Spectrum
CY25402SXCT	CYPRESS	获取价格	Two PLL Programmable Clock Generator with Spread Spectrum
CY25402SXC-XXX	CYPRESS	获取价格	Two PLL Programmable Clock Generator with Spread Spectrum
CY25402SXC-XXXT	CYPRESS	获取价格	Two PLL Programmable Clock Generator with Spread Spectrum
CY25402SXI	CYPRESS	获取价格	Two PLL Programmable Clock Generator with Spread Spectrum
CY25402SXIT	CYPRESS	获取价格	Two PLL Programmable Clock Generator with Spread Spectrum

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