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CY25100SXC-XXXT

更新时间： 2024-09-29 20:51:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
17页 643K
描述
Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8

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CY25100SXC-XXXT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.17
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.889 mm湿度敏感等级：3
端子数量：8最高工作温度：70 °C
最低工作温度：最大输出时钟频率：200 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3.3 V主时钟/晶体标称频率：166 MHz
认证状态：Not Qualified座面最大高度：1.727 mm
子类别：Clock Generators最大压摆率：35 mA
最大供电电压：3.45 V最小供电电压：3.13 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20宽度：3.8985 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

CY25100SXC-XXXT 数据手册

 浏览型号CY25100SXC-XXXT的Datasheet PDF文件第2页浏览型号CY25100SXC-XXXT的Datasheet PDF文件第3页浏览型号CY25100SXC-XXXT的Datasheet PDF文件第4页浏览型号CY25100SXC-XXXT的Datasheet PDF文件第5页浏览型号CY25100SXC-XXXT的Datasheet PDF文件第6页浏览型号CY25100SXC-XXXT的Datasheet PDF文件第7页 
CY25100  
Field and Factory Programmable Spread  
Spectrum Clock Generator for EMI Reduction  
Field and Factory Programmable Spread Spectrum Clock Generator for EMI Reduction  
Features  
Functional Description  
■ Wide Operating Output (SSCLK) Frequency Range  
❐ 3 MHz to 200 MHz  
The CY25100 is a Spread Spectrum Clock Generator (SSCG) IC  
used to reduce EMI found in today’s high speed digital electronic  
systems.  
■ Programmable Spread Spectrum with nominal 31.5 kHz  
The device uses a Cypress proprietary PLL and Spread  
Spectrum Clock (SSC) technology to synthesize and modulate  
the frequency of the input clock. By frequency modulating the  
clock, the measured EMI at the fundamental and harmonic  
frequencies are greatly reduced. This reduction in radiated  
energy can significantly reduce the cost of complying with  
regulatory agency (EMC) requirements and improve  
time-to-market without degrading system performance.  
Modulation Frequency  
❐ Center Spread: ±0.25% to ±2.5%  
❐ Down Spread: –0.5% to –5.0%  
■ Input frequency range  
❐ External Crystal: 8 to 30 MHz Fundamental Crystals  
❐ External Reference: 8 to 166 MHz Clock  
■ Integrated Phase-Locked Loop (PLL)  
■ Field Programmable devices available  
■ Programmable Crystal Load Capacitor Tuning Array  
■ Low Cycle-to-cycle Jitter  
The CY25100 uses  
a
factory or field-programmable  
configuration memory array to synthesize output frequency,  
spread percentage, crystal load capacitor, reference clock output  
on/off, spread spectrum on/off function, and PD#/OE options.  
The spread percentage is programmed to either center spread  
or down spread with various spread percentages. The range for  
center spread is from ±0.25% to ±2.50%. The range for down  
spread is from –0.5% to –5.0%.  
■ Spread Spectrum on/off function  
■ Powerdown or Output Enable function  
■ Commercial and Industrial temperature ranges  
■ 3.3 V operation  
The input to the CY25100 can either be a crystal or a clock  
signal. The CY25100 has two clock outputs: REFCLK and  
SSCLK. The non-spread spectrum REFCLK output has the  
same frequency as the input of the CY25100.  
■ 8-pin TSSOP and SOIC packages  
Logic Block Diagram  
RFB  
PLL  
with  
MODULATION  
CONTROL  
3
XIN  
CXIN  
6
OUTPUT  
DIVIDERS  
and  
PROGRAMMABLE  
CONFIGURATION  
2
REFCLK  
XOUT  
MUX  
CXOUT  
7
4
SSCLK  
PD# or OE  
8
SSON#  
1
5
VDD  
VSS  
Cypress Semiconductor Corporation  
Document #: 38-07499 Rev. *I  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 12, 2011  
[+] Feedback  
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