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CY2509_09 PDF预览

CY2509_09

更新时间: 2024-09-29 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
6页 154K
描述
Spread Aware Ten/Eleven Output Zero Delay Buffer

CY2509_09 数据手册

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CY2509/10  
Spread Aware™, Ten/Eleven Output Zero Delay Buffer  
Features  
Key Specifications  
• Spread Aware™—designed to work with SSFTG  
Operating Voltage: ................................................3.3V±10%  
Operating Range: ....................... 40 MHz < fOUT < 140 MHz  
Cycle-to-Cycle Jitter: ................................................ <100 ps  
Output to Output Skew: ........................................... <100 ps  
Phase Error Jitter:..................................................... <100 ps  
reference signals  
• Well suited to both 100- and 133-MHz designs  
• Ten (CY2509) or eleven (CY2510) LVCMOS/LVTTL  
outputs  
• 50 ps typical peak cycle-to-cycle jitter  
• Single output enable pin for CY2510 version, dual pins  
on CY2509 devices allow shutting down a portion of the  
outputs  
• 3.3V power supply  
• On board 25damping resistors  
• Available in 24-pin TSSOP package  
• Improved tracking skew, but narrower frequency  
support limit when compared to W132-09B/10B  
Block Diagram  
Pin Configurations  
FBIN  
FBOUT  
Q0  
PLL  
AGND  
VDD  
Q0  
Q1  
Q2  
GND  
GND  
Q3  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CLK  
AVDD  
VDD  
Q9  
CLK  
Q1  
Q2  
Q8  
OE0:4  
GND  
GND  
Q7  
Q6  
Q5  
Q3  
Q4  
OE  
Q5  
Q6  
Q7  
Q4  
VDD  
OE  
10  
11  
12  
OE5:8  
VDD  
FBIN  
FBOUT  
Q8  
Q9  
AGND  
VDD  
Q0  
Q1  
Q2  
GND  
GND  
Q3  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CLK  
AVDD  
VDD  
Q8  
Configuration of these blocks dependent upon specific option being used  
Q7  
GND  
GND  
Q6  
Q4  
Q5  
VDD  
OE0:4  
FBOUT  
10  
11  
12  
VDD  
OE5:8  
FBIN  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07230 Rev. *C  
Revised July 01, 2005  

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