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CY2310BNZPVC-1T PDF预览

CY2310BNZPVC-1T

更新时间: 2024-01-21 10:04:49
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 74K
描述
Low Skew Clock Driver, 2310 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, 5.30 MM, SSOP-28

CY2310BNZPVC-1T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP28,.3
针数:28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.82
系列:2310输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:10.2 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.001 A功能数量:1
反相输出次数:端子数量:28
实输出次数:10最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:5 ns
传播延迟(tpd):5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mm最小 fmax:133 MHz
Base Number Matches:1

CY2310BNZPVC-1T 数据手册

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CY2310BNZ  
3.3V SDRAM Buffer for Mobile PCs  
with Four SO-DIMMs  
Description  
Features  
• One input to 10 output buffer/driver  
• Supports up to four SDRAM SO-DIMMs  
• Two additional outputs for feedback  
• SMBus interface for output control  
• Low skew outputs  
The CY2310BNZ is a 3.3V buffer designed to distribute  
high-speed clocks in mobile PC applications. The part has ten  
outputs, eight of which can be used to drive up to four SDRAM  
SO-DIMMs, and the remaining can be used for external  
feedback to a PLL. The device operates at 3.3V and outputs  
can run up to 100 MHz, thus making it compatible with  
Pentium II processors. The CY2310BNZ can be used in  
conjunction with the CY2281 or similar clock synthesizer for a  
full Pentium II motherboard solution.  
• Up to 100 MHz operation  
• Multiple VDD and VSS pins for noise reduction  
• Dedicated OE pin for testing  
• Space-saving 28-pin SSOP package  
• 3.3V operation  
The CY2310BNZ also includes an SMBus interface that can  
enable or disable each output clock. On power-up, all output  
clocks are enabled. A separate Output Enable pin facilitates  
testing on ATE.  
Block Diagram  
Pin Configuration  
28-pin SSOP  
Top View  
BUF_IN  
V
1
DD  
28  
27  
V
DD  
SDRAM7  
SDRAM6  
SDRAM0  
SDRAM1  
2
SDRAM0  
SDRAM1  
3
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
SDRAM2  
SDRAM3  
V
V
4
V
SS  
SS  
5
V
DD  
DD  
SDATA  
6
SDRAM2  
SDRAM3  
SDRAM4  
SDRAM5  
SDRAM6  
SDRAM7  
SDRAM8  
SDRAM5  
SDRAM4  
SMBus  
Decoding  
7
V
8
V
SS  
SS  
9
BUF_IN  
OE  
SCLOCK  
10  
11  
12  
13  
14  
V
V
DD  
DD  
SDRAM8  
SDRAM9  
SDRAM9  
V
V
SS  
SS  
V
V
DDIIC  
SSIIC  
SCLOCK  
SDATA  
OE  
Cypress Semiconductor Corporation  
Document #: 38-07260 Rev. *A  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised January 28, 2003  

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