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CY2310BNZ PDF预览

CY2310BNZ

更新时间: 2024-01-17 14:33:12
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6页 78K
描述
Clocks and Buffers

CY2310BNZ 数据手册

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CY2310BNZ  
3.3V SDRAM Buffer for Mobile PCs  
with Four SO-DIMMs  
Description  
Features  
• One input to 10 output buffer/driver  
• Supports up to four SDRAM SO-DIMMs  
• Two additional outputs for feedback  
• SMBus interface for output control  
• Low skew outputs  
The CY2310BNZ is a 3.3V buffer designed to distribute  
high-speed clocks in mobile PC applications. The part has ten  
outputs, eight of which can be used to drive up to four SDRAM  
SO-DIMMs, and the remaining can be used for external  
feedback to a PLL. The device operates at 3.3V and outputs  
can run up to 100 MHz, thus making it compatible with  
Pentium II processors. The CY2310BNZ can be used in  
conjunction with the CY2281 or similar clock synthesizer for a  
full Pentium II motherboard solution.  
• Up to 100 MHz operation  
• Multiple VDD and VSS pins for noise reduction  
• Dedicated OE pin for testing  
• Space-saving 28-pin SSOP package  
• 3.3V operation  
The CY2310BNZ also includes an SMBus interface that can  
enable or disable each output clock. On power-up, all output  
clocks are enabled. A separate Output Enable pin facilitates  
testing on ATE.  
Block Diagram  
Pin Configuration  
28-pin SSOP  
Top View  
BUF_IN  
V
1
DD  
28  
27  
V
DD  
SDRAM7  
SDRAM6  
SDRAM0  
SDRAM1  
2
SDRAM0  
SDRAM1  
3
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
SDRAM2  
SDRAM3  
V
V
4
V
SS  
SS  
5
V
DD  
DD  
SDATA  
6
SDRAM2  
SDRAM3  
SDRAM4  
SDRAM5  
SDRAM6  
SDRAM7  
SDRAM8  
SDRAM5  
SDRAM4  
SMBus  
Decoding  
7
V
8
V
SS  
SS  
9
BUF_IN  
OE  
SCLOCK  
10  
11  
12  
13  
14  
V
V
DD  
DD  
SDRAM8  
SDRAM9  
SDRAM9  
V
V
SS  
SS  
V
V
DDIIC  
SSIIC  
SCLOCK  
SDATA  
OE  
Cypress Semiconductor Corporation  
Document #: 38-07260 Rev. *A  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised January 28, 2003  

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