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CY2310ANZPVXC-1 PDF预览

CY2310ANZPVXC-1

更新时间: 2024-11-08 21:54:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 动态存储器PC
页数 文件大小 规格书
15页 303K
描述
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs

CY2310ANZPVXC-1 数据手册

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1CY7C139  
fax id: 5204  
CY7C138  
CY7C139  
4K x 8/9 Dual-Port Static RAM  
are included on the CY7C138/9 to handle situations when mul-  
tiple processors access the same piece of data. Two ports are  
provided permitting independent, asynchronous access for  
reads and writes to any location in memory. The CY7C138/9  
can be utilized as a standalone 8/9-bit dual-port static RAM or  
multiple devices can be combined in order to function as a  
16/18-bit or wider master/slave dual-port static RAM. An M/S  
pin is provided for implementing 16/18-bit or wider memory  
applications without the need for separate master and slave  
devices or additional discrete logic. Application areas include  
interprocessor/multiprocessor designs, communications sta-  
tus buffering, and dual-port video/graphics memory.  
Features  
• True Dual-Ported memory cells which allow  
simultaneous reads of the same memory location  
• 4K x 8 organization (CY7C138)  
• 4K x 9 organization (CY7C139)  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
• Low operating power: I = 160 mA (max.)  
CC  
• Fully asynchronous operation  
• Automatic power-down  
• TTL compatible  
• Expandable data bus to 32/36 bits or more using  
Master/Slave chip select when using more than one  
device  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
Each port has independent control pins: chip enable (CE),  
read or write enable (R/W), and output enable (OE). Twoflags are  
provided on each port (BUSY and INT). BUSY signals that the port is  
trying to access the same location currently being accessed by the  
other port. The interrupt flag (INT) permits communication between  
ports or systems by means of a mail box. The semaphores are used  
to pass a flag, or token, from one port to the other to indicate that a  
shared resource is in use. The semaphore logic is comprised of eight  
shared latches. Only one side can control the latch (semaphore) at  
any time. Control of a semaphore indicates that a shared resource is  
in use. An automatic power-down feature is controlled independently  
on each port by a chip enable (CE) pin or SEM pin.  
• INT flag for port-to-port communication  
• Available in 68-pin PLCC  
Functional Description  
The CY7C138 and CY7C139 are available in a 68-pin PLCC.  
The CY7C138 and CY7C139 are high-speed CMOS 4K x 8  
and 4K x 9 dual-port static RAMs. Various arbitration schemes  
Logic BlockDiagram  
R/W  
L
R/W  
R
CE  
L
CE  
R
OE  
OE  
R
L
I/O  
I/O  
(7C139)  
BUSY  
8L  
7L  
I/O (7C139)  
7R  
8R  
I/O  
I/O  
CONTROL  
I/O  
CONTROL  
I/O  
0L  
I/O  
0R  
[1, 2]  
R
[1, 2]  
BUSY  
L
A
11L  
A
11R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
MEMORY  
ARRAY  
A
0L  
A
0R  
INTERRUPT  
SEMAPHORE  
ARBITRATION  
CE  
R
CE  
L
OE  
R
OE  
L
R/W  
R
R/W  
L
SEM  
SEM  
R
L
[2]  
[2]  
INT  
C138-1  
INT  
R
L
M/S  
Notes:  
1. BUSY is an output in master mode and an input in slave mode.  
2. Interrupt: push-pull output and requires no pull-up resistor.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
November 1996  

CY2310ANZPVXC-1 替代型号

型号 品牌 替代类型 描述 数据表
CY2310ANZPVC-1T CYPRESS

完全替代

3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
CY2310ANZPVC-1 CYPRESS

完全替代

3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
CDC319DB TI

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1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

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