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CY2310ANZ_09 PDF预览

CY2310ANZ_09

更新时间: 2024-02-25 07:48:04
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 动态存储器PC
页数 文件大小 规格书
9页 254K
描述
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs

CY2310ANZ_09 数据手册

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CY2310ANZ  
3.3V SDRAM Buffer for Mobile PCs  
with 4 SO-DIMMs  
Features  
Functional Description  
One input to 10 output buffer and driver  
Supports up to four SDRAM SO-DIMMs  
Two additional outputs for feedback  
Serial interface for output control  
Low skew outputs  
The CY2310ANZ is a 3.3V buffer designed to distribute high  
speed clocks in mobile PC applications. The part has 10 outputs,  
eight of which are used to drive up to four SDRAM SO-DIMMs.  
The remaining are used for external feedback to a PLL. The  
device operates at 3.3V and outputs can run up to 100 MHz, thus  
making it compatible with Pentium II® processors. The  
CY2310ANZ can be used in conjunction with the CY2281 or  
similar clock synthesizer for a full Pentium II motherboard  
solution.  
Up to 100 MHz operation  
The CY2310ANZ also includes a serial interface which can  
enable or disable each output clock. During power up, all output  
clocks are enabled. A separate Output Enable pin facilitates  
testing on ATE.  
Multiple VDD and VSS pins for noise reduction  
Dedicated OE pin for testing  
Space saving 28-pin SSOP package  
3.3V operation  
Logic Block Diagram  
BUF_IN  
SDRAM0  
SDRAM1  
SDRAM2  
SDRAM3  
SDATA  
SDRAM4  
Serial Interface  
SDRAM5  
SDRAM6  
SDRAM7  
SDRAM8  
Decoding  
SCLOCK  
SDRAM9  
OE  
Cypress Semiconductor Corporation  
Document #: 38-07142 Rev. *C  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Revised January 12, 2009  
[+] Feedback  

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