Datasheet > CY2308AZC-1H

CY2308AZC-1H

更新时间： 2024-11-20 15:30:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
8页	69K
描述
PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16

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CY2308AZC-1H 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.12	系列：	2308
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0	长度：	5 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	16
实输出次数：	8	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.2 ns	座面最大高度：	1.1 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm	最小 fmax：	200 MHz
Base Number Matches：	1

CY2308AZC-1H 数据手册

CY2308A

Eight-Output, 200-MHz Zero Delay Buffer

Features

Functional Description

• 50-MHz to 200-MHz operating range

The CY2308A is a high-performance 200-MHz zero delay

buffer designed for high-speed clock distribution. The

• 650-ps Total Timing Budget (TTB ) window

• Multiple configurations (see Table 2)

• Eight low-skew outputs

integrated PLL is designed for low jitter and optimized for noise

rejection. These parameters are critical for reference clock

distribution in systems using high-performance ASICs and

microprocessors. The CY2308A PLL feedback is external and

is required to be driven into the FBK pin using anyone of the

outputs.

— Output-output skew < 200 ps

— Device-device skew < 500 ps

• Input-output skew < 250 ps

• Three-stateable outputs

The device features a guaranteed maximum TTB window

specifying all occurrences of output clocks with respect to the

input reference clock across variations in output frequency,

supply voltage, operating temperature, input edge rate, and

process.

• < 50-µA shutdown current

• Phase-locked loop (PLL) bypass mode (see Table 1)

• Spread Aware

The CY2308A has two banks of four outputs each that can be

controlled by the Select inputs as shown in Table 1. If all output

clocks are not required, Bank B can be three-stated. The

select inputs also allow the input clock to be directly applied to

the output for chip and system testing purposes.

• 16-pin TSSOP

• 3.3V operation

• Commercial/Industrial temperature

The CY2308A PLL enters a power-down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off, resulting in less than

50 µA of current draw. The PLL shuts down in two additional

cases, as shown in Table 1.

The CY2308A is available in five different configurations, as

shown in Table 2. The CY2308A–1 is the base part with the

output frequencies equal to the reference if there is no divider

in the feedback path. The CY2308A–1H is the high-drive

version of the –1 with faster rise and fall times.

The CY2308A–2 allows the user to obtain 1X / ½X frequencies

on each output bank. The exact configuration and output

frequencies depends on which output drives FBK.

Pin Configuration

Block Diagram

TSSOP

Top View

FBK

PLL

REF

MUX

REF

FBK

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKA1

CLKA2

CLKB2

GND

CLKA3

CLKA4

CLKB3

Select Input

Decoding

CLKB4

CLKB1

CLKB2

CLKB3

CLKB4

Extra Divider (–2)

Cypress Semiconductor Corporation

Document #: 38-07377 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised March 5, 2003

12 3 4 5 6 7 8

中文翻译

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与CY2308AZC-1H相关器件

型号	品牌	获取价格	描述	数据表
CY2308AZC-1T	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2308AZI-1H	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2308AZI-1HT	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2308AZI-2	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2308AZI-2T	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2308SC-1	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-1H	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-1HT	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-1T	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-2	CYPRESS	获取价格	3.3V Zero Delay Buffer

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