Datasheet > CY2308_12

CY2308_12

更新时间： 2024-11-20 12:21:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	604K
描述
3.3 V Zero Delay Buffer

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CY2308_12 数据手册

CY2308

3.3 V Zero Delay Buffer

3.3

V Zero Delay Buffer

The CY2308 has two banks of four outputs each that is controlled

by the select inputs as shown in the table Select Input Decoding

on page 3. If all output clocks are not required, Bank B is

three-stated. The input clock is directly applied to the output for

chip and system testing purposes by the select inputs.

Features

■ Zero input-output propagation delay, adjustable by capacitive

load on FBK input

■ Multiple configurations, see Available CY2308 Configurations

on page 4 for more details

The CY2308 PLL enters a power down state when there are no

rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off resulting in less than 25 A

of current draw. The PLL shuts down in two additional cases as

shown in the table Select Input Decoding on page 3.

■ Multiple low skew outputs

■ Two banks of four outputs, three-stateable by two select inputs

■ 10 MHz to 133 MHz operating range

■ 75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)

■ Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP

■ 3.3 V operation

Multiple CY2308 devices accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is less than 700 ps.

The CY2308 is available in five different configurations as shown

in the table Available CY2308 Configurations on page 4.

■ The CY2308-1 is the base part where the output frequencies

equal the reference if there is no counter in the feedback path.

The CY2308-1H is the high drive version of the -1 and rise and

fall times on this device are much faster.

■ Industrial temperature available

Functional Description

The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute

high speed clocks in PC, workstation, datacom, telecom, and

other high performance applications.

■ TheCY2308-2enablestheusertoobtain2xand1xfrequencies

on each output bank. The exact configuration and output

frequencies depend on the user’s selection of output that drives

the feedback pin.

The part has an on-chip PLL that locks to an input clock

presented on the REF pin. The PLL feedback is driven from

external FBK pin, so user has flexibility to choose any one of the

outputs as feedback input and connect it to FBK pin. The

input-to-output skew is less than 250 ps and output-to-output

skew is less than 200 ps.

■ TheCY2308-3enablestheusertoobtain4xand2xfrequencies

on the outputs.

■ The CY2308-4 enables the user to obtain 2x clocks on all

outputs. Thus, the part is extremely versatile and is used in a

variety of applications.

■ The CY2308-5H is a high drive version with REF/2 on both

banks.

Logic Block Diagram

FBK

PLL

REF

MUX

CLKA1

CLKA2

CLKA3

CLKA4

Extra Divider (–3, –4)

Extra Divider (–5H)

Select Input

Decoding

CLKB1

CLKB2

CLKB3

CLKB4

Extra Divider (–2, –3)

Cypress Semiconductor Corporation

Document Number: 38-07146 Rev. *M

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 11, 2011

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与CY2308_12相关器件

型号	品牌	获取价格	描述	数据表
CY2308-1	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308-1H	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308-2	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308-3	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308-4	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308-5H	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308AZC-1	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2308AZC-1H	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2308AZC-1T	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2308AZI-1H	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,

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