Datasheet > CY2308

CY2308

更新时间： 2024-11-19 22:50:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	203K
描述
3.3V Zero Delay Buffer

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CY2308 数据手册

1CY2308

CY2308

3.3V Zero Delay Buffer

The CY2308 has two banks of four outputs each, which can

be controlled by the Select inputs as shown in the table “Select

Input Decoding.” If all output clocks are not required, Bank B

can be three-stated. The select inputs also allow the input

clock to be directly applied to the output for chip and system

testing purposes.

Features

• Zero input-output propagation delay, adjustable by

capacitive load on FBK input

• Multiple configurations, see “Available CY2308

Configurations” table

• Multiple low-skew outputs

— Output-output skew less than 200 ps

— Device-device skew less than 700 ps

The CY2308 PLL enters a power-down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off, resulting in less than

50 µA of current draw. The PLL shuts down in two additional

cases as shown in the “Select Input Decoding” table.

Multiple CY2308 devices can accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.

The CY2308 is available in five different configurations, as

shown in the “Available CY2308 Configurations” table on page

2. The CY2308–1 is the base part, where the output

frequencies equal the reference if there is no counter in the

feedback path. The CY2308–1H is the high-drive version of

the –1, and rise and fall times on this device are much faster.

— Two banks of four outputs, three-stateable by two

select inputs

• 10-MHz to 133-MHz operating range

• Low jitter, less than 200 ps cycle-cycle (–1, –1H, –4, –5H)

• Space-saving 16-pin 150-mil SOIC package or 16-pin

TSSOP

• 3.3V operation

• Industrial Temperature available

The CY2308–2 allows the user to obtain 2X and 1X

frequencies on each output bank. The exact configuration and

output frequencies depends on which output drives the

feedback pin. The CY2308–3 allows the user to obtain 4X and

2X frequencies on the outputs.

The CY2308–4 enables the user to obtain 2X clocks on all

outputs. Thus, the part is extremely versatile, and can be used

in a variety of applications.

Functional Description

The CY2308 is a 3.3V Zero Delay Buffer designed to distribute

high-speed clocks in PC, workstation, datacom, telecom, and

other high-performance applications.

The part has an on-chip PLL which locks to an input clock

presented on the REF pin. The PLL feedback is required to be

driven into the FBK pin, and can be obtained from one of the

outputs. The input-to-output skew is guaranteed to be less

than 350 ps, and output-to-output skew is guaranteed to be

less than 200 ps.

The CY2308–5H is a high-drive version with REF/2 on both

banks.

Pin Configuration

Block Diagram

FBK

PLL

SOIC

REF

MUX

Top View

CLKA1

CLKA2

CLKA3

CLKA4

REF

CLKA1

FBK

Extra Divider (–3, –4)

Extra Divider (–5H)

CLKA4

CLKA3

V_DD

CLKA2

V_DD

GND

CLKB1

Select Input

CLKB4

CLKB3

Decoding

CLKB2

CLKB1

CLKB2

CLKB3

CLKB4

Extra Divider (–2, –3)

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07146 Rev. *C

Revised June 16, 2004

12 3 4 5 6 7...14

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与CY2308相关器件

型号	品牌	获取价格	描述	数据表
CY2308_07	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308_08	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308_09	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308_12	CYPRESS	获取价格	3.3 V Zero Delay Buffer
CY2308-1	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308-1H	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308-2	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308-3	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308-4	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308-5H	CYPRESS	获取价格	3.3V Zero Delay Buffer

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