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CY2305ZC-1T PDF预览

CY2305ZC-1T

更新时间： 2024-11-19 22:07:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 203K
描述
LOW-COST 3.3V ZERO DELAY BUFFER

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中文翻译

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CY2305ZC-1T 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：TSSOP, TSSOP8,.25
针数：8Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.61
系列：2305输入调节：MUX
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：4.4 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
最大I（ol）：0.008 A功能数量：1
反相输出次数：端子数量：8
实输出次数：4最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：240
电源：3.3 VProp。Delay @ Nom-Sup：0.35 ns
传播延迟（tpd）：8.7 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.25 ns座面最大高度：1.1 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3 mm
最小 fmax：133.33 MHzBase Number Matches：1

CY2305ZC-1T 数据手册

 浏览型号CY2305ZC-1T的Datasheet PDF文件第2页浏览型号CY2305ZC-1T的Datasheet PDF文件第3页浏览型号CY2305ZC-1T的Datasheet PDF文件第4页浏览型号CY2305ZC-1T的Datasheet PDF文件第5页浏览型号CY2305ZC-1T的Datasheet PDF文件第6页浏览型号CY2305ZC-1T的Datasheet PDF文件第7页 
CY2305  
CY2309  
Low-cost 3.3V Zero Delay Buffer  
up to 100-/133-MHz frequencies, and have higher drive than  
the -1 devices. All parts have on-chip PLLs which lock to an  
input clock on the REF pin. The PLL feedback is on-chip and  
is obtained from the CLKOUT pad.  
Features  
• 10-MHz to 100-/133-MHz operating range, compatible  
with CPU and PCI bus frequencies  
• Zero input-output propagation delay  
• Multiple low-skew outputs  
The CY2309 has two banks of four outputs each, which can  
be controlled by the Select inputs as shown in the “Select Input  
Decoding” table on page 2. If all output clocks are not required,  
BankB can be three-stated. The select inputs also allow the  
input clock to be directly applied to the outputs for chip and  
system testing purposes.  
— Output-output skew less than 250 ps  
— Device-device skew less than 700 ps  
— One input drives five outputs (CY2305)  
The CY2305 and CY2309 PLLs enter a power-down mode  
when there are no rising edges on the REF input. In this state,  
the outputs are three-stated and the PLL is turned off, resulting  
in less than 12.0 µA of current draw for commercial temper-  
ature devices and 25.0 µA for industrial temperature parts. The  
CY2309 PLL shuts down in one additional case as shown in  
the table below.  
— One input drives nine outputs, grouped as 4 + 4 + 1  
(CY2309)  
• Less than 200 ps cycle-cycle jitter, compatible with  
Pentium -based systems  
• Test Mode to bypass phase-locked loop (PLL) (CY2309  
only [see “Select Input Decoding” on page 2])  
Multiple CY2305 and CY2309 devices can accept the same  
input clock and distribute it. In this case, the skew between the  
outputs of two devices is guaranteed to be less than 700 ps.  
• Available in space-saving 16-pin 150-mil SOIC or  
4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil  
SOIC package (CY2305)  
All outputs have less than 200 ps of cycle-cycle jitter. The input  
to output propagation delay on both devices is guaranteed to  
be less than 350 ps, and the output to output skew is  
guaranteed to be less than 250 ps.  
• 3.3V operation  
• Industrial temperature available  
Functional Description  
The CY2305/CY2309 is available in two/three different config-  
urations, as shown in the ordering information (page 10). The  
CY2305-1/CY2309-1 is the base part. The CY2305-1H/  
CY2309-1H is the high-drive version of the -1, and its rise and  
fall times are much faster than the -1s.  
The CY2309 is a low-cost 3.3V zero delay buffer designed to  
distribute high-speed clocks and is available in a 16-pin SOIC  
or TSSOP package. The CY2305 is an 8-pin version of the  
CY2309. It accepts one reference input, and drives out five  
low-skew clocks. The -1H versions of each device operate at  
Block Diagram  
Pin Configuration  
SOIC/TSSOP  
Top View  
CLKOUT  
PLL  
MUX  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
REF  
CLKOUT  
REF  
CLKA1  
CLKA2  
CLKA1  
CLKA4  
CLKA3  
CLKA2  
V
V
DD  
DD  
GND  
GND  
CLKA3  
CLKA4  
CLKB4  
CLKB3  
S1  
CLKB1  
CLKB2  
S2  
2309-2  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
S2  
SOIC  
Top View  
Select Input  
Decoding  
1
8
CLKOUT  
CLK4  
V
DD  
REF  
CLK2  
CLK1  
GND  
S1  
2
3
4
7
6
2309-3  
2309-1  
5
CLK3  
Cypress Semiconductor Corporation  
Document #: 38-07140 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised December 14, 2002  
1234567...13

中文翻译

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