CY2305CSXC-1T

更新时间： 2024-11-20 04:12:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
14页	309K
描述
3.3V Zero Delay Clock Buffer

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替代型号

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CY2305CSXC-1T 数据手册

CY2305C

CY2309C

PRELIMINARY

3.3V Zero Delay Clock Buffer

CY2309C. It accepts one reference input and drives out five low

skew clocks. The -1H versions of each device operate up to

100-133 MHz frequencies and have higher drive than the -1

devices. All parts have on-chip PLLs which lock to an input clock

on the REF pin. The PLL feedback is on-chip and is obtained

from the CLKOUT pad.

Features

■ 10 MHz to 100-133 MHz operating range, compatiblewith CPU

and PCI bus frequencies

■ Zero input and output propagation delay

■ Multiple low skew outputs

The CY2309C has two banks of four outputs each that are

controlled by the select inputs as shown in the “Select Input

Decoding for CY2309C” on page 3. If all output clocks are not

required, BankB is three-stated. The input clock is directly

applied to the outputs by the select inputs for chip and system

testing purposes.

■ One input drives five outputs (CY2305C)

■ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)

■ 50 ps typical cycle-cycle jitter (15 pF, 66 MHz)

■ Test Mode to bypass phase locked loop (PLL) (CY2309C) only,

see “Select Input Decoding for CY2309C” on page 3

The CY2305C and CY2309C PLLs enter a power down mode

when there are no rising edges on the REF input. In this state,

the outputs are three-stated and the PLL is turned off. This

results in less than 12.0 μA of current draw for commercial

temperature devices and 25.0 μA for industrial temperature

parts. The CY2309C PLL shuts down in one additional case as

shown in the “Select Input Decoding for CY2309C” on page 3.

■ Available in space saving 16-pin 150 Mil SOIC or 4.4 mm

TSSOP packages (CY2309C), and 8-pin, 150 Mil SOIC

package (CY2305C)

■ 3.3V operation

In the special case when S2:S1 is 1:0, the PLL is bypassed and

REF is output from DC to the maximum allowable frequency. The

part behaves like a non-zero delay buffer in this mode and the

outputs are not three-stated.

■ Industrial temperature available

Functional Description

The CY2305C and CY2309C are die replacement parts for

CY2305 and CY2309.

The CY2305C or CY2309C is available in two or three different

configurations as shown in the “Ordering Information” on

page 11. The CY2305C-1 or CY2309C-1 is the base part. The

CY2305-1H or CY2309-1H is the high drive version of the -1. Its

rise and fall times are much faster than the -1s.

The CY2309C is a low cost 3.3V zero delay buffer designed to

distribute high speed clocks and is available in a 16-pin SOIC or

TSSOP package. The CY2305C is an 8-pin version of the

Logic Block Diagram for CY2309C

CLKOUT

MUX

PLL

REF

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Select Input

Decoding

Cypress Semiconductor Corporation

Document Number: 38-07672 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 5, 2007

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CY2305CSXC-1T 替代型号

型号	品牌	替代类型	描述	数据表
CY2305CSXC-1H	CYPRESS	完全替代	3.3V Zero Delay Clock Buffer
CY2305SXI-1H	CYPRESS	类似代替	Low-Cost 3.3V Zero Delay Buffer

与CY2305CSXC-1T相关器件

型号	品牌	获取价格	描述	数据表
CY2305CSXI-1	CYPRESS	获取价格	3.3V Zero Delay Clock Buffer
CY2305CSXI-1	INFINEON	获取价格	3.3V Zero Delay Buffer
CY2305CSXI-1H	CYPRESS	获取价格	3.3V Zero Delay Clock Buffer
CY2305CSXI-1H	INFINEON	获取价格	3.3V Zero Delay Buffer
CY2305CSXI-1HT	CYPRESS	获取价格	3.3V Zero Delay Clock Buffer
CY2305CSXI-1HT	INFINEON	获取价格	3.3V Zero Delay Buffer
CY2305CSXI-1T	CYPRESS	获取价格	3.3V Zero Delay Clock Buffer
CY2305CSXI-1T	INFINEON	获取价格	3.3V Zero Delay Buffer
CY2305ESXC-1H	CYPRESS	获取价格	Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH
CY2305ESXC-1HT	CYPRESS	获取价格	Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH

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