Datasheet > CY2305_09

CY2305_09

更新时间： 2024-02-01 05:33:52

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
15页	366K
描述
Low Cost 3.3V Zero Delay Buffer

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中文翻译

获取价格

数据手册

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CY2305_09 数据手册

CY2305, CY2309

Low Cost 3.3V Zero Delay Buffer

Features

Functional Description

■

10 MHz to 100/133 MHz operating range, compatible with CPU

and PCI bus frequencies

The CY2309 is a low cost 3.3V zero delay buffer designed to

distribute high speed clocks and is available in a 16-pin SOIC or

TSSOP package. The CY2305 is an 8-pin version of the

CY2309. It accepts one reference input, and drives out five low

skew clocks. The -1H versions of each device operate at up to

100-/133 MHz frequencies, and have higher drive than the -1

devices. All parts have on-chip PLLs which lock to an input clock

on the REF pin. The PLL feedback is on-chip and is obtained

from the CLKOUT pad.

■

Zero input-output propagation delay

60 ps typical cycle-to-cycle jitter (high drive)

Multiple low skew outputs

❐

85 ps typical output-to-output skew

One input drives five outputs (CY2305)

One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)

The CY2309 has two banks of four outputs each, which can be

controlled by the select inputs as shown in the “Select Input

Decoding” table on page 3. If all output clocks are not required,

BankB can be three-stated. The select inputs also allow the input

clock to be directly applied to the outputs for chip and system

testing purposes.

■

Compatible with Pentium-based systems

Test Mode to bypass phase-locked loop (PLL) (CY2309 only

[see “Select Input Decoding” on page 3])

■

Available in space-saving 16-pin 150-mil SOIC or 4.4-mm

TSSOPpackages(CY2309), and8-pin, 150-milSOICpackage

(CY2305)

The CY2305 and CY2309 PLLs enter a power down mode when

there are no rising edges on the REF input. In this state, the

outputs are three-stated and the PLL is turned off, resulting in

less than 25.0 μA current draw for these parts. The CY2309 PLL

shuts down in one additional case as shown in the table below.

■

3.3V operation

Industrial temperature available

Multiple CY2305 and CY2309 devices can accept the same input

clock and distribute it. In this case, the skew between the outputs

of two devices is guaranteed to be less than 700 ps.

The CY2305/CY2309 is available in two/three different

configurations, as shown in the ordering information (page 10).

The CY2305-1/CY2309-1 is the base part. The CY2305-1H/

CY2309-1H is the high drive version of the -1, and its rise and

fall times are much faster than the -1s.

Logic Block Diagram

CLKOUT

MUX

PLL

REF

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

Select Input

Decoding

CLKB2

CLKB3

CLKB4

Cypress Semiconductor Corporation

Document #: 38-07140 Rev. *J

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised March 12, 2009

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中文翻译

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与CY2305_09相关器件

型号	品牌	获取价格	描述	数据表
CY2305_11	CYPRESS	获取价格	Low Cost 3.3-V Zero Delay Buffer
CY2305_12	CYPRESS	获取价格	3.3 V Zero Delay Clock Buffer
CY2305C	CYPRESS	获取价格	Zero Delay Buffers
CY2305C_07	CYPRESS	获取价格	3.3V Zero Delay Clock Buffer
CY2305C_09	CYPRESS	获取价格	3.3V Zero Delay Clock Buffer
CY2305C_11	CYPRESS	获取价格	3.3 V Zero Delay Clock Buffer
CY2305C-1	CYPRESS	获取价格	Zero Delay Buffers
CY2305C-1H	CYPRESS	获取价格	Zero Delay Buffers
CY2305CSXA-1	CYPRESS	获取价格	3.3V Zero Delay Clock Buffer
CY2305CSXA-1H	CYPRESS	获取价格	3.3V Zero Delay Clock Buffer

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